General-purpose timers (TIM15/TIM16/TIM17) RM0440
1392/2126 RM0440 Rev 4
30.7.2 TIM15 control register 2 (TIM15_CR2)
Address offset: 0x04
Reset value: 0x0000
Bit 2 URS: Update request source
This bit is set and cleared by software to select the UEV event sources.
0: Any of the following events generate an update interrupt if enabled. These events can be:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
1: Only counter overflow/underflow generates an update interrupt if enabled
Bit 1 UDIS: Update disable
This bit is set and cleared by software to enable/disable UEV event generation.
0:UEV enabled. The Update (UEV) event is generated by one of the following events:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
Buffered registers are then loaded with their preload values.
1:UEV disabled. The Update event is not generated, shadow registers keep their value
(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is
set or if a hardware reset is received from the slave mode controller.
Bit 0 CEN: Counter enable
0: Counter disabled
1: Counter enabled
Note: External clock and gated mode can work only if the CEN bit has been previously set by
software. However trigger mode can set the CEN bit automatically by hardware.
1514131211109876543210
Res. Res. Res. Res. Res. OIS2 OIS1N OIS1 TI1S MMS[2:0] CCDS CCUS Res. CCPC
rw rw rw rw rw rw rw rw rw rw
Bits 15:11 Reserved, must be kept at reset value.
Bit 10 OIS2: Output idle state 2 (tim_oc2 output)
0: tim_oc2=0 when MOE=0
1: tim_oc2=1 when MOE=0
Note: This bit cannot be modified as long as LOCK level 1, 2 or 3 has been programmed
(LOCK bits in the TIM15_BKR register).
Bit 9 OIS1N: Output Idle state 1 (tim_oc1n output)
0: tim_oc1n=0 after a dead-time when MOE=0
1: tim_oc1n=1 after a dead-time when MOE=0
Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed
(LOCK bits in TIM15_BKR register).
Bit 8 OIS1: Output Idle state 1 (tim_oc1 output)
0: tim_oc1=0 after a dead-time when MOE=0
1: tim_oc1=1 after a dead-time when MOE=0
Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed
(LOCK bits in TIM15_BKR register).
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