ST STM32G473 User Manual

Basic timers (TIM6/TIM7) RM0440
1462/2126 RM0440 Rev 4
31.4.7 TIMx prescaler (TIMx_PSC)(x = 6 to 7)
Address offset: 0x28
Reset value: 0x0000
31.4.8 TIMx auto-reload register (TIMx_ARR)(x = 6 to 7)
Address offset: 0x2C
Reset value: 0x0000 FFFF
Bit 31 UIFCPY: UIF copy
This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in
TIMx_CR1 is reset, bit 31 is reserved and read as 0.
Bits 30:16 Reserved, must be kept at reset value.
Bits 15:0 CNT[15:0]: Counter value
Non-dithering mode (DITHEN = 0)
The register holds the counter value.
Dithering mode (DITHEN = 1)
The register only holds the non-dithered part in CNT[15:0]. The fractional part is not
available.
1514131211109876543210
PSC[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 15:0 PSC[15:0]: Prescaler value
The counter clock frequency f
tim_cnt_ck
is equal to f
tim_psc_ck
/ (PSC[15:0] + 1).
PSC contains the value to be loaded into the active prescaler register at each update event.
(including when the counter is cleared through UG bit of TIMx_EGR register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ARR[19:16]
rw rw rw rw
1514131211109876543210
ARR[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:20 Reserved, must be kept at reset value.
Bits 19:0 ARR[19:0]: Auto-reload value
ARR is the value to be loaded into the actual auto-reload register.
Refer to Section 31.3.4: Time-base unit on page 1448 for more details about ARR update
and behavior.
The counter is blocked while the auto-reload value is null.
Non-dithering mode (DITHEN = 0)
The register holds the auto-reload value in ARR[15:0]. The ARR[19:16] bits are reserved.
Dithering mode (DITHEN = 1)
The register holds the integer part in ARR[19:4]. The ARR[3:0] bitfield contains the dithered
part.

ST STM32G473 Specifications

General

Brand	ST
Model	STM32G473
Category	Microcontrollers
Language	English