RM0440 Rev 4 1461/2126
RM0440 Basic timers (TIM6/TIM7)
1463
31.4.4 TIMx status register (TIMx_SR)(x = 6 to 7)
Address offset: 0x10
Reset value: 0x0000
31.4.5 TIMx event generation register (TIMx_EGR)(x = 6 to 7)
Address offset: 0x14
Reset value: 0x0000
31.4.6 TIMx counter (TIMx_CNT)(x = 6 to 7)
Address offset: 0x24
Reset value: 0x0000 0000
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. UIF
rc_w0
Bits 15:1 Reserved, must be kept at reset value.
Bit 0 UIF: Update interrupt flag
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
– On counter overflow if UDIS = 0 in the TIMx_CR1 register.
– When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if
URS = 0 and UDIS = 0 in the TIMx_CR1 register.
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Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. UG
w
Bits 15:1 Reserved, must be kept at reset value.
Bit 0 UG: Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action.
1: Re-initializes the timer counter and generates an update of the registers. Note that the
prescaler counter is cleared too (but the prescaler ratio is not affected).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIF
CPY
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
r
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CNT[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
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