RM0440 Rev 4 1589/2126
RM0440 Tamper and backup registers (TAMP)
1592
36.6.6 TAMP masked interrupt status register (TAMP_MISR)
Address offset: 0x34
Backup domain reset value: 0x0000 0000
System reset: not affected
Bits 31:24 Reserved, must be kept at reset value.
Bit 23 Reserved, must be kept at reset value.
Bit 22 Reserved, must be kept at reset value.
Bit 21 ITAMP6F: ST manufacturer readout tamper detection flag
This flag is set by hardware when a tamper detection event is detected on the internal
tamper 6.
Bit 20 ITAMP5F: RTC calendar overflow tamper detection flag
This flag is set by hardware when a tamper detection event is detected on the internal
tamper 5.
Bit 19 ITAMP4F: HSE monitoring tamper detection flag
This flag is set by hardware when a tamper detection event is detected on the internal
tamper 4.
Bit 18 ITAMP3F: LSE monitoring tamper detection flag
This flag is set by hardware when a tamper detection event is detected on the internal
tamper 3.
Bit 17 Reserved, must be kept at reset value.
Bit 16 Reserved, must be kept at reset value.
Bits 15:3 Reserved, must be kept at reset value.
Bit 2 TAMP3F: TAMP3 detection flag
This flag is set by hardware when a tamper detection event is detected on the TAMP3 input.
Bit 1 TAMP2F: TAMP2 detection flag
This flag is set by hardware when a tamper detection event is detected on the TAMP2 input.
Bit 0 TAMP1F: TAMP1 detection flag
This flag is set by hardware when a tamper detection event is detected on the TAMP1 input.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
ITAMP6
MF
ITAMP5
MF
ITAMP4
MF
ITAMP3
MF
Res. Res.
r
r
rr
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
TAMP
3MF
TAMP
2MF
TAMP
1MF
r
rr
Bits 31:24 Reserved, must be kept at reset value.
Bit 23 Reserved, must be kept at reset value.
Bit 22 Reserved, must be kept at reset value.
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