ST STM32G473 User Manual

RM0440 Rev 4 293/2126
RM0440 Reset and clock control (RCC)
338
7.4.4 PLL configuration register (RCC_PLLCFGR)
Address offset: 0x0C
Reset value: 0x0000 1000
Access: no wait state, word, half-word and byte access
This register is used to configure the PLL clock outputs according to the formulas:
• f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
• f(PLL_P) = f(VCO clock) / PLLP
• f(PLL_Q) = f(VCO clock) / PLLQ
• f(PLL_R) = f(VCO clock) / PLLR
Bits 3:2 SWS[1:0]: System clock switch status
Set and cleared by hardware to indicate which clock source is used as system clock.
00: Reserved, must be kept at reset value
01: HSI16 oscillator used as system clock
10: HSE used as system clock
11: PLL used as system clock
Bits 1:0 SW[1:0]: System clock switch
Set and cleared by software to select system clock source (SYSCLK).
Configured by hardware to force HSI16 oscillator selection when exiting stop and standby
modes or in case of failure of the HSE oscillator.
00: Reserved, must be kept at reset value
01: HSI16 selected as system clock
10: HSE selected as system clock
11: PLL selected as system clock
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLPDIV[4:0] PLLR[1:0]
PLL
REN
Res. PLLQ[1:0]
PLL
QEN
Res. Res. PLLP
PLL
PEN
rw rw rw rw rw rw rw rw rw rw rw rw rw
1514131211109 8 7 65432 1 0
Res. PLLN[6:0] PLLM[3:0] Res. Res. PLLSRC[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:27 PLLPDIV[4:0]: Main PLLP division factor
Set and cleared by software to control the PLL “P” frequency. PLL “P” output clock frequency
= VCO frequency / PLLPDIV.
00000: PLL “P” clock is controlled by the bit PLLP
00001: Reserved.
00010: PLL “P” clock = VCO / 2
....
11111: PLL “P” clock = VCO / 31

ST STM32G473 Specifications

General

Brand	ST
Model	STM32G473
Category	Microcontrollers
Language	English