ST STM32G473 User Manual

Reset and clock control (RCC) RM0440
294/2126 RM0440 Rev 4
Bits 26:25 PLLR[1:0]: Main PLL division factor for PLL “R” clock (system clock)
Set and cleared by software to control the frequency of the main PLL output clock PLLCLK.
This output can be selected as system clock. These bits can be written only if PLL is
disabled.
PLL “R” output clock frequency = VCO frequency / PLLR with PLLR = 2, 4, 6, or 8
00: PLLR = 2
01: PLLR = 4
10: PLLR = 6
11: PLLR = 8
Caution: The software has to set these bits correctly not to exceed 170 MHz on
this domain.
Bit 24 PLLREN: PLL “R” clock output enable
Set and reset by software to enable the PLL “R” clock output of the PLL (used as system
clock).
This bit cannot be written when PLL “R” clock output of the PLL is used as System Clock.
In order to save power, when the PLL “R” clock output of the PLL is not used, the value of
PLLREN should be 0.
0: PLL “R” clock output disable
1: PLL “R” clock output enable
Bit 23 Reserved, must be kept at reset value.
Bits 22:21 PLLQ[1:0]: Main PLL division factor for PLL “Q” clock.
Set and cleared by software to control the frequency of the main PLL output clock PLL “Q”
clock. This output can be selected for USB, RNG, SAI (48 MHz clock). These bits can be
written only if PLL is disabled.
PLL “Q” output clock frequency = VCO frequency / PLLQ with PLLQ = 2, 4, 6, or 8
00: PLLQ = 2
01: PLLQ = 4
10: PLLQ = 6
11: PLLQ = 8
Caution: The software has to set these bits correctly not to exceed 170 MHz on
this domain.
Bit 20 PLLQEN: Main PLL “Q” clock output enable
Set and reset by software to enable the PLL “Q” clock output of the PLL.
In order to save power, when the PLL “Q” clock output of the PLL is not used, the value of
PLLQEN should be 0.
0: PLL “Q” clock output disable
1: PLL “Q” clock output enable
Bits 19:18 Reserved, must be kept at reset value.
Bit 17 PLLP: Main PLL division factor for PLL “P” clock.
Set and cleared by software to control the frequency of the main PLL output clock PLL “P”
clock. These bits can be written only if PLL is disabled.
When the PLLPDIV[4:0] is set to “00000”PLL “P” output clock frequency = VCO frequency /
PLLP with PLLP =7, or 17
0: PLLP = 7
1: PLLP = 17
Caution: The software has to set these bits correctly not to exceed 170 MHz on
this domain.

ST STM32G473 Specifications

General

Brand	ST
Model	STM32G473
Category	Microcontrollers
Language	English