RM0440 Rev 4 553/2126
RM0440 Flexible static memory controller (FSMC)
571
Bits 29:28 ACCMOD[1:0]: Access mode
Specifies the asynchronous access modes as shown in the timing diagrams. These bits are
taken into account only when the EXTMOD bit in the FMC_BCRx register is 1.
00: Access mode A
01: Access mode B
10: Access mode C
11: Access mode D
Bits 27:24 DATLAT[3:0]: (see note below bit descriptions): Data latency for synchronous memory
For synchronous access with read/write Burst mode enabled (BURSTEN / CBURSTRW bits
set), defines the number of memory clock cycles (+2) to issue to the memory before
reading/writing the first data:
This timing parameter is not expressed in HCLK periods, but in FMC_CLK periods.
For asynchronous access, this value is don't care.
0000: Data latency of 2 CLK clock cycles for first burst access
1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset)
Bits 23:20 CLKDIV[3:0]: Clock divide ratio (for FMC_CLK signal)
Defines the period of FMC_CLK clock output signal, expressed in number of HCLK cycles:
0000: FMC_CLK period= 1x HCLK period
0001: FMC_CLK period = 2 × HCLK periods
0010: FMC_CLK period = 3 × HCLK periods
1111: FMC_CLK period = 16 × HCLK periods (default value after reset)
In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is don’t care.
Note: Refer to Section 19.6.5: Synchronous transactions for FMC_CLK divider ratio formula)
Bits 19:16 BUSTURN[3:0]: Bus turnaround phase duration
These bits are written by software to add a delay at the end of current read or write
transaction to next transaction on the same bank.
This delay allows to match the minimum time between consecutive transactions (t
EHEL
from
NEx high to NEx low) and the maximum time needed by the memory to free the data bus
after a read access (t
EHQZ
, chip enable high to output Hi-Z). This delay is recommended for
mode D and muxed mode. For non-muxed memory, the bus turnaround delay can be set to
minimum value.
(BUSTURN + 1)HCLK period ≥ max(t
EHEL
min, t
EHQZ
max)
For FRAM memories, the bus turnaround delay should be configured to match the minimum
tPC (precharge time) timings. The bus turnaround delay is inserted between any consecutive
transactions on the same bank (read/read, write/write, read/write and write/read) to match the
tPC memory timing. The chip select is toggling between any consecutive accesses.
(BUSTURN + 1)HCLK period ≥ t
PC
min
0000: BUSTURN phase duration = 1 HCLK clock cycle added
...
1111: BUSTURN phase duration = 16 x HCLK clock cycles added (default value after reset)
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