ST STM32G473 User Manual

List of figures RM0440
60/2126 RM0440 Rev 4
Figure 101. Example of JSQR queue of context with overflow before conversion . . . . . . . . . . . . . . . 637
Figure 102. Example of JSQR queue of context with overflow during conversion . . . . . . . . . . . . . . . 637
Figure 103. Example of JSQR queue of context with empty queue (case JQM=0). . . . . . . . . . . . . . . 638
Figure 104. Example of JSQR queue of context with empty queue (case JQM=1). . . . . . . . . . . . . . . 639
Figure 105. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0).
Case when JADSTP occurs during an ongoing conversion. . . . . . . . . . . . . . . . . . . . . . . 639
Figure 106. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0).
Case when JADSTP occurs during an ongoing conversion and a new
trigger occurs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640
Figure 107. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0).
Case when JADSTP occurs outside an ongoing conversion . . . . . . . . . . . . . . . . . . . . . . 640
Figure 108. Flushing JSQR queue of context by setting JADSTP=1 (JQM=1) . . . . . . . . . . . . . . . . . . 641
Figure 109. Flushing JSQR queue of context by setting ADDIS=1 (JQM=0). . . . . . . . . . . . . . . . . . . . 641
Figure 110. Flushing JSQR queue of context by setting ADDIS=1 (JQM=1). . . . . . . . . . . . . . . . . . . . 642
Figure 111. Single conversions of a sequence, software trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644
Figure 112. Continuous conversion of a sequence, software trigger . . . . . . . . . . . . . . . . . . . . . . . . . . 644
Figure 113. Single conversions of a sequence, hardware trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645
Figure 114. Continuous conversions of a sequence, hardware trigger . . . . . . . . . . . . . . . . . . . . . . . . 645
Figure 115. Right alignment (offset disabled, unsigned value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647
Figure 116. Right alignment (offset enabled, signed value). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648
Figure 117. Left alignment (offset disabled, unsigned value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648
Figure 118. Left alignment (offset enabled, signed value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649
Figure 119. Example of overrun (OVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650
Figure 120. AUTODLY=1, regular conversion in continuous mode, software trigger . . . . . . . . . . . . . 653
Figure 121. AUTODLY=1, regular HW conversions interrupted by injected conversions
(DISCEN=0; JDISCEN=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654
Figure 122. AUTODLY=1, regular HW conversions interrupted by injected conversions . . . . . . . . . . . . .
(DISCEN=1, JDISCEN=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655
Figure 123. AUTODLY=1, regular continuous conversions interrupted by injected conversions . . . . 656
Figure 124. AUTODLY=1 in auto- injected mode (JAUTO=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656
Figure 125. Analog watchdog guarded area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
Figure 126. ADCy_AWDx_OUT signal generation (on all regular channels). . . . . . . . . . . . . . . . . . . . 659
Figure 127. ADCy_AWDx_OUT signal generation (AWDx flag not cleared by software) . . . . . . . . . . 660
Figure 128. ADCy_AWDx_OUT signal generation (on a single regular channel) . . . . . . . . . . . . . . . . 660
Figure 129. ADCy_AWDx_OUT signal generation (on all injected channels) . . . . . . . . . . . . . . . . . . . 660
Figure 130. 20-bit to 16-bit result truncation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662
Figure 131. Numerical example with 5-bit shift and rounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662
Figure 132. Triggered regular oversampling mode (TROVS bit = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 664
Figure 133. Regular oversampling modes (4x ratio) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
65
Figure 134. Regular and injected oversampling modes used simultaneously . . . . . . . . . . . . . . . . . . . 665
Figure 135. Triggered regular oversampling with injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666
Figure 136. Oversampling in auto-injected mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666
Figure 137. Dual ADC block diagram
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669
Figure 138. Injected simultaneous mode on 4 channels: dual ADC mode . . . . . . . . . . . . . . . . . . . . . 670
Figure 139. Regular simultaneous mode on 16 channels: dual ADC mode . . . . . . . . . . . . . . . . . . . . 672
Figure 140. Interleaved mode on 1 channel in continuous conversion mode: dual ADC mode. . . . . . 673
Figure 141. Interleaved mode on 1 channel in single conversion mode: dual ADC mode. . . . . . . . . . 674
Figure 142. Interleaved conversion with injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674
Figure 143. Alternate trigger: injected group of each ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675
Figure 144. Alternate trigger: 4 injected channels (each ADC) in discontinuous mode . . . . . . . . . . . . 676
Figure 145. Alternate + regular simultaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677
Figure 146. Case of trigger occurring during injected conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677

ST STM32G473 Specifications

General

Brand	ST
Model	STM32G473
Category	Microcontrollers
Language	English