ST STM32G473 User Manual

RM0440 Rev 4 61/2126
RM0440 List of figures
71
Figure 147. Interleaved single channel CH0 with injected sequence CH11, CH12 . . . . . . . . . . . . . . . 678
Figure 148. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12
- case 1: Master interrupted first . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678
Figure 149. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12
- case 2: Slave interrupted first . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678
Figure 150. DMA Requests in regular simultaneous mode when MDMA=0b00 . . . . . . . . . . . . . . . . . 679
Figure 151. DMA requests in regular simultaneous mode when MDMA=0b10 . . . . . . . . . . . . . . . . . . 680
Figure 152. DMA requests in interleaved mode when MDMA=0b10 . . . . . . . . . . . . . . . . . . . . . . . . . . 680
Figure 153. Temperature sensor channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682
Figure 154. VBAT channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683
Figure 155. VREFINT channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684
Figure 156. Dual-channel DAC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727
Figure 157. Data registers in single DAC channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734
Figure 158. Data registers in dual DAC channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735
Figure 159. Timing diagram for conversion with trigger disabled TEN = 0 . . . . . . . . . . . . . . . . . . . . . 737
Figure 160. DAC LFSR register calculation algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739
Figure 161. DAC conversion (SW trigger enabled) with LFSR wave generation. . . . . . . . . . . . . . . . . 739
Figure 162. DAC triangle wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740
Figure 163. DAC conversion (SW trigger enabled) with triangle wave generation . . . . . . . . . . . . . . . 740
Figure 164. DAC sawtooth wave generation (STDIRx=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741
Figure 165. DAC sawtooth wave generation (STDIRx=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741
Figure 166. DAC sawtooth STINCTRIG and STRSTTRIG priority (STDIR = 0) . . . . . . . . . . . . . . . . . 742
Figure 167. DAC Sample and hold mode phase diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744
Figure 168. Comparator block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778
Figure 169. Comparator hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780
Figure 170. Comparator output blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781
Figure 171. Standalone mode: external gain setting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789
Figure 172. Follower configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790
Figure 173. PGA mode, internal gain setting (x2/x4/x8/x16/x32/x64),
inverting input not used. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791
Figure 174. PGA mode, internal gain setting (x2/x4/x8/x16/x32/x64),
inverting input used for filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792
Figure 175. PGA mode, non-inverting gain setting (x2/x4/x8/x16/x32/x64)
or inverting gain setting (x-1/x-3/x-7/x-15/x-31/x-63) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793
Figure 176. PGA mode, non-inverting gain setting (x2/x4/x8/x16/x32/x64)
or inverting gain setting (x-1/x-3/x-7/x-15/x-31/x-63) with filtering . . . . . . . . . . . . . . . . . . 794
Figure 177. Example configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794
Figure 178. Timer controlled Multiplexer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797
Figure 179. RNG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831
Figure 180. Entropy source model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832
Figure 181. RNG initialization overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835
Figure 182. High-resolution timer overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847
Figure 183. Counter and capture register format vs clock prescaling factor . . . . . . . . . . . . . . . . . . . . 853
Figure 184. Timer A..F overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855
Figure 185. Continuous timer operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 857
Figure 186. Single-shot timer operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 857
Figure 187. Timer reset resynchronization (prescaling ratio above 32). . . . . . . . . . . . . . . . . . . . . . . . 859
Figure 188. Repetition rate versus HRTIM_REPxR content in continuous mode . . . . . . . . . . . . . . . . 860
Figure 189. Repetition counter behavior in single-shot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860
Figure 190. Compare events action on outputs: set on compare 1, reset on compare 2 . . . . . . . . . . 862
Figure 191. Timer A timing unit capture circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866
Figure 192. Auto-delayed overview (compare 2 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867

ST STM32G473 Specifications

General

Brand	ST
Model	STM32G473
Category	Microcontrollers
Language	English