Analog-to-digital converters (ADC) RM0440
620/2126 RM0440 Rev 4
21.4.12 Channel-wise programmable sampling time (SMPR1, SMPR2)
Before starting a conversion, the ADC must establish a direct connection between the
voltage source under measurement and the embedded sampling capacitor of the ADC. This
sampling time must be enough for the input voltage source to charge the embedded
capacitor to the input voltage level.
Each channel can be sampled with a different sampling time which is programmable using
the SMP[2:0] bits in the ADC_SMPR1 and ADC registers. It is therefore possible to select
among the following sampling time values:
• SMP = 000: 2.5 ADC clock cycles
• SMP = 001: 6.5 ADC clock cycles
• SMP = 010: 12.5 ADC clock cycles
• SMP = 011: 24.5 ADC clock cycles
• SMP = 100: 47.5 ADC clock cycles
• SMP = 101: 92.5 ADC clock cycles
• SMP = 110: 247.5 ADC clock cycles
• SMP = 111: 640.5 ADC clock cycles
The total conversion time is calculated as follows:
T
CONV
= Sampling time + 12.5 ADC clock cycles
Example:
With F
adc_ker_ck
= 30 MHz and a sampling time of 2.5 ADC clock cycles:
T
CONV
= (2.5 + 12.5) ADC clock cycles = 15 ADC clock cycles = 500 ns
The ADC notifies the end of the sampling phase by setting the status bit EOSMP (only for
regular conversion).
Constraints on the sampling time
For each channel, SMP[2:0] bits must be programmed to respect a minimum sampling time
as specified in the ADC characteristics section of the datasheets.
Bulb sampling mode
When the BULB bit is set in ADC register, the sampling period starts immediately after the
last ADC conversion. A hardware or software trigger starts the conversion after the sampling
time has been programmed in ADC_SMPR1 register. The very first ADC conversion, after
the ADC is enabled, is performed with the sampling time programmed in SMP bits. The Bulb
mode is effective starting from the second conversion.
The maximum sampling time is limited (refer to the ADC characteristics section of the
datasheet).
The Bulb mode is neither compatible with the continuous conversion mode nor with the
injected channel conversion.
When the BULB bit is set, it is not allowed to set SMPTRIG bit in ADC_CFGR2.
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