ST STM32G473 User Manual

RM0440 Rev 4 619/2126
RM0440 Analog-to-digital converters (ADC)
724
The software can write the register ADC_JSQR at any time, when the ADC is enabled
(ADEN=1). Refer to Section 21.6.16: ADC injected sequence register (ADC_JSQR) for
additional details.
Note: There is no hardware protection to prevent these forbidden write accesses and ADC
behavior may become in an unknown state. To recover from this situation, the ADC must be
disabled (clear ADEN=0 as well as all the bits of ADC_CR register).
21.4.11 Channel selection (SQRx, JSQRx)
There are up to 19 multiplexed channels per ADC:
• Up to 13 slow analog inputs coming from GPIO pads (ADCx_INP/INN[6:18])
Depending on the products, not all of them are available on GPIO pads.
• The ADCs are connected to the following internal analog inputs:
– The internal reference voltage (V
REFINT
) is connected to ADC1_INP18,
ADC3_INP18, ADC4_INP18 and ADC5_INP18.
– The internal temperature sensor (V
TS
) is connected to ADC1_INP16 and
ADC5_INP4.
–The V
BAT
monitoring channel (V
BAT
/3) is connected to ADC1_INP17,
ADC3_INP17 and ADC5_INP17.
Note: To convert one of the internal analog channels, the corresponding analog sources must first
be enabled by programming bits VREFEN, VBATSEL or VSENSESEL in the ADCx_CCR
registers.
It is possible to organize the conversions in two groups: regular and injected. A group
consists of a sequence of conversions that can be done on any channel and in any order.
For instance, it is possible to implement the conversion sequence in the following order:
ADCx_INP/INN3, ADCx_INP/INN8, ADCx_INP/INN2, ADCx_INN/INP2, ADCx_INP/INN0,
ADCx_INP/INN2, ADCx_INP/INN2, ADCx_INP/INN15.
• A regular group is composed of up to 16 conversions. The regular channels and their
order in the conversion sequence must be selected in the ADC_SQRy registers. The
total number of conversions in the regular group must be written in the L[3:0] bits in the
ADC_SQR1 register.
• An injected group is composed of up to 4 conversions. The injected channels and
their order in the conversion sequence must be selected in the ADC_JSQR register.
The total number of conversions in the injected group must be written in the L[1:0] bits
in the ADC_JSQR register.
ADC_SQRy registers must not be modified while regular conversions can occur. For this,
the ADC regular conversions must be first stopped by writing ADSTP=1 (refer to
Section 21.4.17: Stopping an ongoing conversion (ADSTP, JADSTP)).
The software is allowed to modify on-the-fly the ADC_JSQR register when JADSTART is set
to 1 (injected conversions ongoing) only when the context queue is enabled (JQDIS=0 in
ADC_CFGR register). Refer to Section 21.4.21: Queue of context for injected conversions

ST STM32G473 Specifications

General

Brand	ST
Model	STM32G473
Category	Microcontrollers
Language	English