List of figures RM0440
64/2126 RM0440 Rev 4
Figure 295. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1111
Figure 296. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . 1111
Figure 297. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1112
Figure 298. Output stage of capture/compare channel (channel 1, idem ch. 2, 3 and 4) . . . . . . . . . 1112
Figure 299. Output stage of capture/compare channel (channel 5, idem ch. 6) . . . . . . . . . . . . . . . . 1113
Figure 300. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1115
Figure 301. Output compare mode, toggle on tim_oc1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1117
Figure 302. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1118
Figure 303. Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1119
Figure 304. Dithering principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1120
Figure 305. Data format and register coding in dithering mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1121
Figure 306. PWM resolution vs frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1122
Figure 307. PWM dithering pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1123
Figure 308. Dithering effect on duty cycle in center-aligned PWM mode . . . . . . . . . . . . . . . . . . . . . 1124
Figure 309. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . . . . . . . . . . . . . . 1126
Figure 310. Combined PWM mode on channel 1 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1127
Figure 311. 3-phase combined PWM signals with multiple trigger pulses per period . . . . . . . . . . . . 1128
Figure 312. Complementary output with symmetrical dead-time insertion . . . . . . . . . . . . . . . . . . . . 1129
Figure 313. Asymmetrical deadtime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1130
Figure 314. Dead-time waveforms with delay greater than the negative pulse . . . . . . . . . . . . . . . . . 1130
Figure 315. Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . 1130
Figure 316. Break and Break2 circuitry overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1133
Figure 317. Various output behavior in response to a break event on tim_brk (OSSI = 1) . . . . . . . . 1135
Figure 318. PWM output state following tim_brk and tim_brk2 assertion (OSSI=1) . . . . . . . . . . . . . 1136
Figure 319. PWM output state following tim_brk assertion (OSSI=0) . . . . . . . . . . . . . . . . . . . . . . . . 1137
Figure 320. Output redirection (tim_brk2 request not represented). . . . . . . . . . . . . . . . . . . . . . . . . . 1138
Figure 321. tim_ocref_clr input selection multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1139
Figure 322. Clearing TIMx tim_ocxref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1140
Figure 323. 6-step generation, COM example (OSSR=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1141
Figure 324. Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1142
Figure 325. Retriggerable one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1143
Figure 326. Pulse generator circuitry . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1144
Figure 327. Pulse generation on compare event, for edge-aligned and encoder modes . . . . . . . . . 1145
Figure 328. Extended pulsewidth in case of concurrent triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1146
Figure 329. Example of counter operation in encoder interface mode. . . . . . . . . . . . . . . . . . . . . . . . 1148
Figure 330. Example of encoder interface mode with tim_ti1fp1 polarity inverted. . . . . . . . . . . . . . . 1148
Figure 331. Quadrature encoder counting modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1149
Figure 332. Direction plus clock encoder mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1150
Figure 333. Directional clock encoder mode (CC1P = CC2P = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1150
Figure 334. Directional clock encoder mode (CC1P = CC2P = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1151
Figure 335. Index gating options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1152
Figure 336. Jittered Index signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1152
Figure 337. Index generation for IPOS[1:0] = 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1153
Figure 338. Counter reading with index gated on channel A (IPOS[1:0] = 11) . . . . . . . . . . . . . . . . . 1154
Figure 339. Counter reading with index ungated (IPOS[1:0] = 00) . . . . . . . . . . . . . . . . . . . . . . . . . . 1154
Figure 340. Counter reading with index gated on channel A and B. . . . . . . . . . . . . . . . . . . . . . . . . . 1155
Figure 341. Encoder mode behavior in case of narrow index pulse (IPOS[1:0] = 11) . . . . . . . . . . . . 1156
Figure 342. Counter reset Narrow index pulse (closer view, ARR = 0x07) . . . . . . . . . . . . . . . . . . . . 1157
Figure 343. Index behavior in x1 and x2 mode (IPOS[1:0] = 01). . . . . . . . . . . . . . . . . . . . . . . . . . . . 1158
Figure 344. Directional index sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1159
Figure 345. Counter reset as function of FIDX bit setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1159
Figure 346. Index behavior in clock + direction mode, IPOS[0] = 1. . . . . . . . . . . . . . . . . . . . . . . . . . 1160
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