ST STM32G473 User Manual

RM0440 Rev 4 65/2126
RM0440 List of figures
71
Figure 347. Index behavior in directional clock mode, IPOS[0] = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 1160
Figure 348. State diagram for quadrature encoded signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1161
Figure 349. Up-counting encoder error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1162
Figure 350. Down-counting encode error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1163
Figure 351. Encoder mode change with preload transferred on update (SMSPS = 0) . . . . . . . . . . . 1164
Figure 352. Measuring time interval between edges on 3 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 1165
Figure 353. Example of Hall sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1167
Figure 354. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1168
Figure 355. Control circuit in Gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1169
Figure 356. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1170
Figure 357. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . 1171
Figure 358. General-purpose timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1229
Figure 359. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . 1235
Figure 360. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . 1236
Figure 361. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1237
Figure 362. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1237
Figure 363. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1238
Figure 364. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1238
Figure 365. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . 1239
Figure 366. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . 1240
Figure 367. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1241
Figure 368. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1242
Figure 369. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1242
Figure 370. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1243
Figure 371. Counter timing diagram, Update event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1243
Figure 372. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . . . . . . . . . . . 1245
Figure 373. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1245
Figure 374. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . 1246
Figure 375. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1246
Figure 376. Counter timing diagram, Update event with ARPE=1 (co
unter underflow). . . . . . . . . . . 1247
Figure 377. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . 1248
Figure 378. Control circuit in normal mode, internal clock divided by 1. . . . . . . . . . . . . . . . . . . . . . . 1249
Figure 379. tim_ti2 external clock connection example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1249
Figure 380. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1250
Figure 381. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1251
Figure 382. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1252
Figure 383. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . 1252
Figure 384. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1253
Figure 385. Output stage of capture/compare channel (channel 1, idem ch.2, 3 and 4) . . . . . . . . . . 1253
Figure 386. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1256
Figure 387. Output compare mode, toggle on tim_oc1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1258
Figure 388. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1259
Figure 389. Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1260
Figure 390. Dithering principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1261
Figure 391. Data format and register coding in dithering mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1262
Figure 392. PWM resolution vs frequency (16-bit mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1263
Figure 393. PWM resolution vs frequency (32-bit mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1263
Figure 394. PWM dithering pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1264
Figure 395. Dithering effect on duty cycle in center-aligned PWM mode . . . . . . . . . . . . . . . . . . . . . 1265
Figure 396. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . . . . . . . . . . . . . . 1267
Figure 397. Combined PWM mode on channels 1 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1268
Figure 398. OCREF_CLR input selection multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1269

ST STM32G473 Specifications

General

Brand	ST
Model	STM32G473
Category	Microcontrollers
Language	English