ST STM32G473 User Manual

List of figures RM0440
66/2126 RM0440 Rev 4
Figure 399. Clearing TIMx tim_ocxref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1269
Figure 400. Example of one-pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1270
Figure 401. Retriggerable one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1272
Figure 402. Pulse generator circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1272
Figure 403. Pulse generation on compare event, for edge-aligned and encoder modes . . . . . . . . . 1273
Figure 404. Extended pulse width in case of concurrent triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . 1274
Figure 405. Example of counter operation in encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . 1276
Figure 406. Example of encoder interface mode with tim_ti1fp1 polarity inverted . . . . . . . . . . . . . . 1276
Figure 407. Quadrature encoder counting modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1277
Figure 408. Direction plus clock encoder mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1278
Figure 409. Directional clock encoder mode (CC1P = CC2P = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1279
Figure 410. Directional clock encoder mode (CC1P = CC2P = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1279
Figure 411. Index gating options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1281
Figure 412. Jittered Index signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1281
Figure 413. Index generation for IPOS[1:0] = 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1282
Figure 414. Counter reading with index gated on channel A (IPOS[1:0] = 11) . . . . . . . . . . . . . . . . . 1282
Figure 415. Counter reading with index ungated (IPOS[1:0] = 00) . . . . . . . . . . . . . . . . . . . . . . . . . . 1283
Figure 416. Counter reading with index gated on channel A and B. . . . . . . . . . . . . . . . . . . . . . . . . . 1283
Figure 417. Encoder mode behavior in case of narrow index pulse (IPOS[1:0] = 11) . . . . . . . . . . . . 1284
Figure 418. Counter reset Narrow index pulse (closer view, ARR = 0x07) . . . . . . . . . . . . . . . . . . . . 1285
Figure 419. Index behavior in x1 and x2 mode (IPOS[1:0] = 01). . . . . . . . . . . . . . . . . . . . . . . . . . . . 1286
Figure 420. Directional index sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1287
Figure 421. Counter reset as function of FIDX bit setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1287
Figure 422. Index behavior in clock + direction mode, IPOS[0] = 1. . . . . . . . . . . . . . . . . . . . . . . . . . 1288
Figure 423. Index behavior in directional clock mode, IPOS[0] = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 1288
Figure 424. State diagram for quadrature encoded signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1289
Figure 425. Up-counting encoder error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1290
Figure 426. Down-counting encode error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1291
Figure 427. Encoder mode change with preload transferred on update (SMSPS = 0) . . . . . . . . . . . 1292
Figure 428. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1294
Figure 429. Control circuit in gated mode . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1295
Figure 430. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1295
Figure 431. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . 1297
Figure 432. Master/Slave timer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1297
Figure 433. Master/slave connection example with 1 channel only timers . . . . . . . . . . . . . . . . . . . . 1298
Figure 434. Gating TIM_slv with tim_oc1ref of TIM_mstr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1299
Figure 435. Gating TIM_slv with Enable of TIM_mstr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1300
Figure 436. Triggering TIM_slv with update of TIM_mstr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1301
Figure 437. Triggering TIM_slv with Enable of TIM_mstr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1301
Figure 438. Triggering TIM_mstr and TIM_slv with TIM_mstr tim_ti1 input . . . . . . . . . . . . . . . . . . . . 1302
Figure 439. TIM15 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1346
Figure 440. TIM16/TIM17 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1347
Figure 441. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . 1352
Figure 442. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . 1352
Figure 443. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1354
Figure 444. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1354
Figure 445. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1355
Figure 446. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1355
Figure 447. Counter timing diagram, update event when ARPE=0
(TIMx_ARR not preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1356
Figure 448. Counter timing diagram, update event when ARPE=1
(TIMx_ARR preloaded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1357

ST STM32G473 Specifications

General

Brand	ST
Model	STM32G473
Category	Microcontrollers
Language	English