ST STM32G473 User Manual

RM0440 Rev 4 67/2126
RM0440 List of figures
71
Figure 449. Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . 1358
Figure 450. Control circuit in normal mode, internal clock divided by 1. . . . . . . . . . . . . . . . . . . . . . . 1359
Figure 451. tim_ti2 external clock connection example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1359
Figure 452. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1360
Figure 453. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . 1361
Figure 454. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1361
Figure 455. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . 1362
Figure 456. Output stage of capture/compare channel (channel 2 for TIM15) . . . . . . . . . . . . . . . . . 1362
Figure 457. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1365
Figure 458. Output compare mode, toggle on tim_oc1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1367
Figure 459. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1368
Figure 460. Dithering principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1369
Figure 461. Data format and register coding in dithering mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1369
Figure 462. PWM resolution vs frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1370
Figure 463. PWM dithering pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1371
Figure 464. Combined PWM mode on channel 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1373
Figure 465. Complementary output with symmetrical dead-time insertion. . . . . . . . . . . . . . . . . . . . . 1374
Figure 466. Asymmetrical deadtime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1375
Figure 467. Dead-time waveforms with delay greater than the negative pulse. . . . . . . . . . . . . . . . . 1375
Figure 468. Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . 1375
Figure 469. Break circuitry overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1377
Figure 470. Output behavior in response to a break event on tim_brk . . . . . . . . . . . . . . . . . . . . . . . 1379
Figure 471. Output redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1381
Figure 472. tim_ocref_clr input selection multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1381
Figure 473. Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1382
Figure 474. Retriggerable one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1384
Figure 475. Measuring time interval between edges on 2 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 1384
Figure 476. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1385
Figure 477. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1386
Figure 478. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1387
Figure 479. Basic timer block diagram. . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1447
Figure 480. Control circuit in normal mode, internal clock divided by 1. . . . . . . . . . . . . . . . . . . . . . . 1448
Figure 481. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . 1449
Figure 482. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . 1450
Figure 483. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1451
Figure 484. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1451
Figure 485. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1452
Figure 486. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1452
Figure 487. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1453
Figure 488. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1454
Figure 489. Dithering principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1455
Figure 490. Data format and register coding in dithering mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1455
Figure 491. FCnt resolution vs frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1456
Figure 492. PWM dithering pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1456
Figure 493. Low-power timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1465
Figure 494. Glitch filter timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1468
Figure 495. LPTIM output waveform, single counting mode configuration . . . . . . . . . . . . . . . . . . . . 1469
Figure 496. LPTIM output waveform, Single counting mode configuration
and Set-once mode activated (WAVE bit is set). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1470
Figure 497. LPTIM output waveform, Continuous counting mode configuration . . . . . . . . . . . . . . . . 1470

ST STM32G473 Specifications

General

Brand	ST
Model	STM32G473
Category	Microcontrollers
Language	English