ST STM32G473 User Manual

General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0440
1326/2126 RM0440 Rev 4
29.5.14 TIMx prescaler (TIMx_PSC)(x = 2 to 5)
Address offset: 0x028
Reset value: 0x0000
29.5.15 TIMx auto-reload register (TIMx_ARR)(x = 3, 4)
Address offset: 0x02C
Reset value: 0xFFFF FFFF
Bit 31 CNT[31] or UIFCPY: Value depends on IUFREMAP in TIMx_CR1.
If UIFREMAP = 0
CNT[31]: Most significant bit of counter value
If UIFREMAP = 1
UIFCPY: UIF Copy
This bit is a read-only copy of the UIF bit of the TIMx_ISR register
Bits 30:0 CNT[30:0]: Least significant part of counter value
Non-dithering mode (DITHEN = 0)
The register holds the counter value.
Dithering mode (DITHEN = 1)
The register holds the non-dithered part in CNT[30:0]. The fractional part is not available.
1514131211109876543210
PSC[15:0]
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Bits 15:0 PSC[15:0]: Prescaler value
The counter clock frequency tim_cnt_ck is equal to f
tim_psc_ck
/ (PSC[15:0] + 1).
PSC contains the value to be loaded in the active prescaler register at each update event
(including when the counter is cleared through UG bit of TIMx_EGR register or through
trigger controller when configured in “reset mode”).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ARR[19:16]
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1514131211109876543210
ARR[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

ST STM32G473 Specifications

General

Brand	ST
Model	STM32G473
Category	Microcontrollers
Language	English