ST STM32G473 User Manual

Contents RM0440
20/2126 RM0440 Rev 4
22.4.14 Dual DAC channel conversion modes (if dual channels are
available) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747
22.5 DAC low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752
22.6 DAC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752
22.7 DAC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753
22.7.1 DAC control register (DAC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753
22.7.2 DAC software trigger register (DAC_SWTRGR) . . . . . . . . . . . . . . . . . 756
22.7.3 DAC channel1 12-bit right-aligned data holding register
(DAC_DHR12R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757
22.7.4 DAC channel1 12-bit left aligned data holding register
(DAC_DHR12L1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758
22.7.5 DAC channel1 8-bit right aligned data holding register
(DAC_DHR8R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758
22.7.6 DAC channel2 12-bit right aligned data holding register
(DAC_DHR12R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759
22.7.7 DAC channel2 12-bit left aligned data holding register
(DAC_DHR12L2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759
22.7.8 DAC channel2 8-bit right-aligned data holding register
(DAC_DHR8R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760
22.7.9 Dual DAC 12-bit right-aligned data holding register
(DAC_DHR12RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760
22.7.10 Dual DAC 12-bit left aligned data holding register
(DAC_DHR12LD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761
22.7.11 Dual DAC 8-bit right aligned data holding register
(DAC_DHR8RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761
22.7.12 DAC channel1 data output register (DAC_DOR1) . . . . . . . . . . . . . . . . 762
22.7.13 DAC channel2 data output register (DAC_DOR2) . . . . . . . . . . . . . . . . 762
22.7.14 DAC status register (DAC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763
22.7.15 DAC calibration control register (DAC_CCR) . . . . . . . . . . . . . . . . . . . 764
22.7.16 DAC mode control register (DAC_MCR) . . . . . . . . . . . . . . . . . . . . . . . 765
22.7.17 DAC channel1 sample and hold sample time register
(DAC_SHSR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766
22.7.18 DAC channel2 sample and hold sample time register
(DAC_SHSR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767
22.7.19 DAC sample and hold time register (DAC_SHHR) . . . . . . . . . . . . . . . 767
22.7.20 DAC sample and hold refresh time register (DAC_SHRR) . . . . . . . . . 768
22.7.21 DAC channel1 sawtooth register (DAC_STR1) . . . . . . . . . . . . . . . . . . 769
22.7.22 DAC channel2 sawtooth register (DAC_STR2) . . . . . . . . . . . . . . . . . . 769
22.7.23 DAC sawtooth mode register (DAC_STMODR) . . . . . . . . . . . . . . . . . 770
22.7.24 DAC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772

ST STM32G473 Specifications

General

Brand	ST
Model	STM32G473
Category	Microcontrollers
Language	English