To Next Page

To Previous Page

RM0440 Rev 4 593/2126

RM0440 Quad-SPI interface (QUADSPI)

600

20.5.4 QUADSPI flag clear register (QUADSPI_FCR)

Address offset: 0x000C

Reset value: 0x0000 0000

20.5.5 QUADSPI data length register (QUADSPI_DLR)

Address offset: 0x0010

Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CTOF CSMF Res. CTCF CTEF

ww ww

Bits 31:5 Reserved, must be kept at reset value.

Bit 4 CTOF: Clear timeout flag

Writing 1 clears the TOF flag in the QUADSPI_SR register

Bit 3 CSMF: Clear status match flag

Writing 1 clears the SMF flag in the QUADSPI_SR register

Bit 2 Reserved, must be kept at reset value.

Bit 1 CTCF: Clear transfer complete flag

Writing 1 clears the TCF flag in the QUADSPI_SR register

Bit 0 CTEF: Clear transfer error flag

Writing 1 clears the TEF flag in the QUADSPI_SR register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DL[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DL[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

ST STM32G473 User Manual

Questions and Answers: