The PSU2 shelves can be located in the following vertical EQLs: 19,
28, 45, 53 and/or 62.
When the shelf is equipped with PHs to support SIP for Packet
Trunking, any of the PH slots can be used. If a processor group
consists of two SIP PHs, the SIP PHs can either be on the same PSU2
shelf or different shelves. Each shelf that has one or more GQPH
channel groups assigned to it should have at least one spare PH33.
PSU2 shelf power
A separate power bus provides power to each half of a PSU2 shelf.
Refer to Figure 2-15, “PSU2 Shelf Arrangement” (2-27)
Each shelf receives power through six 10 amp fuses. Specifics on the
EQLs and slots powered by each fuse can be found in Table 2-4,
“PSU2 shelf power terminations” (2-27). The table also provides a
reference to the -48V termination.
Table 2-4 PSU2 shelf power terminations
Power
Bus
Shelf EQLs
Powered
Slots Fuse
Value
Back Plane
Termination
A 006-030 PH 0-3 10 amp 02-028-006
A 038-062 PH 4-7 10 amp 02-060-006
A 070-088 PSUCOM 0 10 amp 02-086-006
Figure 2-15 PSU2 Shelf Arrangement
PH Slots PH Slots
PSUCOM 0
006 014
022
030 038
046 054 062 070 078 088 100 110 120 128
136
144
152 160 168 176 184
EQL
PH Slot
Number
0
12
3
4
5
67 8910
11 12
13
14
15
PSUCOM 1
Power Bus - A Power Bus - B
C
F
2
*
C
F
2
*
P
F
2
P
F
2
D
F
2
D
F
2
* Note: the CF2 packs are located in the common shelf only.
Hardware View
Architecture
....................................................................................................................................................................................................................................
235-200-118
Issue 3.02B, March 2007
Lucent Technologies
2-27
To Next Page
Loading...
Need help?
General
