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Renesas RL78/G10 - Registers Used in A;D Converter

Renesas RL78/G10
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RL78/G10 CHAPTER 10 A/D CONVERTER
R01UH0384EJ0311 Rev. 3.11 243
Dec 22, 2016
(5) Successive approximation register (SAR)
The SAR register is a register that sets voltage tap data whose values from the comparison voltage generator match
the voltage values of the analog input pins, 1 bit at a time starting from the most significant bit (MSB).
If data is set in the SAR register all the way to the least significant bit (LSB) (end of A/D conversion), the contents of
the SAR register (conversion results) are held in the A/D conversion result higher-order bit storage register (ADCRH)
and the A/D conversion result lower-order bit storage register (ADCRL). When A/D conversion operations have
ended, an A/D conversion end interrupt request signal (INTAD) is generated.
(6) A/D conversion result higher-order bit storage register (ADCRH)
ADCRH is an 8-bit register which holds the result of A/D conversion. The conversion result is loaded from the
successive approximation register, and the eight higher-order bits of the A/D conversion result are stored in ADCRH.
The two lower-order bits of the result of 10-bit A/D conversion are stored in ADCRL.
(7) A/D conversion result lower-order bit storage register (ADCRL)
ADCRL is an 8-bit register which holds the two lower-order bits (ADCR1, ADCR0) of the result of 10-bit A/D
conversion. The six lower-order bits of this register are fixed to 0.
(8) Controller
This circuit controls the conversion time of an input analog signal that is to be converted into a digital signal, as well
as starting and stopping of the conversion operation. When A/D conversion has been completed, this controller
generates an A/D conversion end interrupt request signal (INTAD).
10.3 Registers Used in A/D Converter
The A/D converter is controlled by the following registers.
Peripheral enable register 0 (PER0)
A/D converter mode register 0 (ADM0)
A/D converter mode register 2 (ADM2)
A/D conversion result higher-order bit storage register (ADCRH)
A/D conversion result lower-order bit storage register (ADCRL)
Analog input channel specification register (ADS)
A/D test register (ADTES)
Port mode register 0 (PM0)
Port mode control register 0 (PMC0)

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