Renesas RL78/G10 User Manual

RL78/G10 CHAPTER 13 SERIAL INTERFACE IICA
R01UH0384EJ0311 Rev. 3.11 429
Dec 22, 2016
13.4.2 Setting transfer clock by using IICWL0 and IICWH0 registers
(1) Setting transfer clock on master side
Transfer clock =
fCLK
IICWL0 + IICWH0 + fCLK (tR + tF)
At this time, the optimal setting values of the IICWL0 and IICWH0 registers are as follows.
(The fractional parts of all setting values are rounded up.)
• When the fast mode
IICWL0 =
0.52
Transfer clock
× fCLK
IICWH0 = (
0.48
Transfer clock
− tR − tF) × fCLK
• When the normal mode
IICWL0 =
0.47
Transfer clock
× fCLK
IICWH0 = (
0.53
Transfer clock
− tR − tF) × fCLK
(2) Setting IICWL0 and IICWH0 registers on slave side
(The fractional parts of all setting values are truncated.)
• When the fast mode
IICWL0 = 1.3
μ s × fCLK
IICWH0 = (1.2
μ s − tR − tF) × fCLK
• When the normal mode
IICWL0 = 4.7
μ s × fCLK
IICWH0 = (5.3
μ s − tR − tF) × fCLK
Caution Note the minimum f
CLK operation frequency when setting the transfer clock. The minimum fCLK
operation frequency for serial interface IICA is determined according to the mode.
Fast mode: f
CLK = 3.5 MHz (MIN.)
Normal mode: f
CLK = 1 MHz (MIN.)
Remarks 1. Calculate the rise time (t
R) and fall time (tF) of the SDAA0 and SCLA0 signals separately, because
they differ depending on the pull-up resistance and wire load.
2. IICWL0: IICA low-level width setting register 0
IICWH0: IICA high-level width setting register 0
t
F: SDAA0 and SCLA0 signal falling times
t
R: SDAA0 and SCLA0 signal rising times
f
CLK: CPU/peripheral hardware clock frequency

Renesas RL78/G10 Specifications

General

Brand	Renesas
Model	RL78/G10
Category	Motherboard
Language	English