RL78/G10 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0384EJ0311 Rev. 3.11 290
Dec 22, 2016
12.3.6 Serial flag clear trigger register 0n (SIR0n)
The SIR0n register is a trigger register that is used to clear each error flag of channel n.
When each bit (FECT0n, PECT0n, OVCT0n) of this register is set to 1, the corresponding bit (FEF0n, PEF0n, OVF0n)
of serial status register 0n (SSR0n) is cleared to 0. Because the SIR0n register is a trigger register, it is cleared
immediately when the corresponding bit of the SSR0n register is cleared.
The SIR0n register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears the SIR0n register to 00H.
Figure 12-8. Format of Serial Flag Clear Trigger Register 0n (SIR0n)
Address: F0108H (SIR00) , F010AH (SIR01) , After reset: 00H R/W
Symbol
7 6 5 4 3 2 1 0
SIR0n
0 0 0 0 0
FECT0n
Note
PECT0n OVCT0n
FECT0n
Note
Clear trigger of framing error of channel n
0 Not cleared
1 Clears the FEF0n bit of the SSR0n register to 0.
PECT0n Clear trigger of parity error flag of channel n
0 Not cleared
1 Clears the PEF0n bit of the SSR0n register to 0.
OVCT0n Clear trigger of overrun error flag of channel n
0 Not cleared
1 Clears the OVF0n bit of the SSR0n register to 0.
Note Provided in the SIR01 register only.
Caution Be sure to clear the following bits to 0.
SIR00 register: Bits 2 to 7
SIR01 register: Bits 3 to 7
Remarks 1. n: Channel number (n = 0, 1)
2. When the SIR0n register is read, 00H is always read.
To Next Page
Loading...
Need help?
General
