Renesas RL78/G10

RL78/G10 CHAPTER 24 ELECTRICAL SPECIFICATIONS
R01UH0384EJ0311 Rev. 3.11 600
Dec 22, 2016
24.5.2 Serial interface IICA
(T
A = −40 to +85°C, 2.0 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions Standard Mode Fast Mode Unit
MIN. MAX. MIN. MAX.
SCLA0 clock frequency fSCL Fast mode: fCLK ≥ 3.5 MHz 0 400 kHz
Standard mode: fCLK ≥ 1 MHz 0 100 kHz
Setup time of restart condition tSU:STA 4.7 0.6 μ s
Hold time
Note 1
tHD:STA 4.0 0.6 μ s
Hold time when SCLA0 = “L” tLOW 4.7 1.3 μ s
Hold time when SCLA0 = “H” tHIGH 4.0 0.6 μ s
Data setup time (reception) tSU:DAT 250 100 ns
Data hold time (transmission)
Note 2
tHD:DAT 0 3.45 0 0.9 μ s
Setup time of stop condition tSU:STO 4.0 0.6 μ s
Bus-free time tBUF 4.7 1.3 μ s
Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected.
2. The maximum value (MAX.) of t
HD:DAT is during normal transfer and a wait state is inserted in the ACK
(acknowledge) timing.
Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up
resistor) at that time in each mode are as follows.
Standard mode: C
b = 400 pF, Rb = 2.7 kΩ
Fast mode: C
b = 200 pF, Rb = 1.7 kΩ
IICA serial transfer timing
t LOW t R
t BUF
t HIGH t F
t HD:STA
Stop
condition
Start
condition
Restart
condition
Stop
condition
t
SU:DAT
t SU:STA t SU:STO t HD:STA
t HD:DAT
SCLA0
SDAA0