Renesas RL78/G10 - Timer Mode Register 0 N (Tmr0 N)

RL78/G10 CHAPTER 6 TIMER ARRAY UNIT
R01UH0384EJ0311 Rev. 3.11 120
Dec 22, 2016
6.3.3 Timer mode register 0n (TMR0n)
The TMR0n register consists of two eight-bit registers (TMR0nH, TMR0nL) which set an operation mode of channel n.
This register is used to select the operation clock (fMCK), select the count clock (fTCLK), select the master/slave, select the
16 or 8-bit timer (only for channels 1 and 3), specify the start trigger and capture trigger, select the valid edge of the timer
input, and specify the operation mode (interval, capture, event counter, one-count, or capture and one-count).
Rewriting the TMR0nH and TMR0nL registers is prohibited when the register is in operation (when TE0n = 1).
The TMR0nH and TMR0nL registers can be set by a 8-bit memory manipulation instruction.
Reset signal generation clears TMR0nH and TMR0nL registers to 00H.
Caution The bits mounted depend on the channels in the bit 3 of TMR0nH register.
TMR02H: MASTER02 bit
TMR01H, TMR03H: SPLIT0n bit (n = 1, 3)
TMR01H: Fixed to 0