RL78/G10 CHAPTER 6 TIMER ARRAY UNIT
R01UH0384EJ0311 Rev. 3.11 121
Dec 22, 2016
Figure 6-8. Format of Timer Mode Register 0n (TMR0n) (1/3)
Address: : F0190H (TMR00L), F0191H (TMR00H) After reset: 00H R/W
: F0192H (TMR01L), F0193H (TMR01H)
: F0194H (TMR02L), F0195H (TMR02H)
: F0196H (TMR03L), F0197H (TMR03H)
Symbol 7 6 5 4 3 2 1 0
TMR00H CKS001 0 0 CCS00 0 STS002 STS001 STS000
Symbol 7 6 5 4 3 2 1 0
TMR02H CKS021 0 0 CCS02 MASTER02 STS022 STS021 STS020
Symbol 7 6 5 4 3 2 1 0
TMR0nH
(n = 1, 3)
CKS0n1 0 0 CCS0n SPLIT0n STS0n2 STS0n1 STS0n0
Symbol 7 6 5 4 3 2 1 0
TMR0nL
(n = 0 to 3)
CIS0n1 CIS0n0 0 0 MD0n3 MD0n2 MD0n1 MD0n0
CKS0n1 Selection of operation clock (fMCK) of channel n
0 Operation clock CK00 set by timer clock select register 0 (TPS0)
1 Operation clock CK01 set by timer clock select register 0 (TPS0)
Operation clock (fMCK) is used by the edge detector. A count clock (fTCLK) and a sampling clock are generated
depending on the setting of the CCS0n bit.
CCS0n Selection of count clock (fTCLK) of channel n
0 Operation clock (fMCK) specified by the CKS0n1 bit
1 Valid edge of input signal input from the TI0n pin
Count clock (fTCLK) is used for the counter, output controller, and interrupt controller.
Cautions 1. Be sure to clear the following bits to 0.
TMR00H register: bits 3, 5, 6
TMR01H to TMR03H registers: bits 5, 6
TMR00L to TMR03L registers: bits 4, 5
2. The timer array unit must be stopped (TT0 = 0FH, TTH0 = 0AH) if the clock selected for
f
CLK is changed (by changing the value of the system clock control register (CKC)),
even if the operating clock (f
MCK) specified by using the CKS0n1 bit or the valid edge of
the signal input from the TI0n pin is selected as the count clock (f
TCLK).
Remark n: Channel number
n = 0, 1 (for 10-pin products); n = 0 to 3 (for 16-pin products)
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