Renesas RL78/G10 - Oscillation Stabilization Time Counter Status Register (OSTC)

RL78/G10 CHAPTER 5 CLOCK GENERATOR
R01UH0384EJ0311 Rev. 3.11 82
Dec 22, 2016
5.3.4 Oscillation stabilization time counter status register (OSTC)
This is the register that indicates the count status of the X1 clock oscillation stabilization time counter.
The X1 clock oscillation stabilization time can be checked in the following case:
• If the X1 clock starts oscillation while the high-speed on-chip oscillator clock is being used as the CPU clock.
• If the STOP mode is entered and then released while the high-speed on-chip oscillator clock is being used as the
CPU clock with the X1 clock oscillating.
The OSTC register can be read by a 1-bit or 8-bit memory manipulation instruction.
When reset signal is generated, the STOP instruction and MSTOP (bit 7 of clock operation status control register
(CSC)) = 1 clear the OSTC register to 00H.
Remark The oscillation stabilization time counter starts counting in the following cases.
• When oscillation of the X1 clock starts (EXCLK, OSCSEL = 0, 1 → MSTOP = 0)
• When the STOP mode is released
Figure 5-5. Format of Oscillation Stabilization Time Counter Status Register (OSTC)
Address: FFFA2H After reset: 00H R
Symbol 7 6 5 4 3 2 1 0
OSTC MOST
8
MOST
9
MOST
10
MOST
11
MOST
13
MOST
15
MOST
17
MOST
18
MOST
8
MOST
9
MOST
10
MOST
11
MOST
13
MOST
15
MOST
17
MOST
18
Oscillation stabilization time status
fX = 10 MHz fX = 20 MHz
0 0 0 0 0 0 0 0 (2
8
+16)/fX max. 27.2 μ s max. 13.6 μ s max.
1 0 0 0 0 0 0 0 (2
8
+16)/fX min. 27.2 μ s min. 13.6 μ s min.
1 1 0 0 0 0 0 0 (2
9
+16)/fX min. 52.8 μ s min. 26.4 μ s min.
1 1 1 0 0 0 0 0 (2
10
+16)/fX min. 104 μ s min. 52.0 μ s min.
1 1 1 1 0 0 0 0 (2
11
+16)/fX min. 206 μ s min. 103 μ s min.
1 1 1 1 1 0 0 0 (2
13
+16)/fX min. 820 μ s min. 410 μ s min.
1 1 1 1 1 1 0 0 (2
15
+16)/fX min. 3.27 ms min. 1.63 ms min.
1 1 1 1 1 1 1 0 (2
17
+16)/fX min. 13.1 ms min. 6.55 ms min.
1 1 1 1 1 1 1 1 (2
18
+16)/fX min. 26.2 ms min. 13.1 ms min.
Cautions 1. After the above time has elapsed, the bits are set to 1 in order from the MOST8 bit
and remain 1.
2. The oscillation stabilization time counter counts up to the oscillation stabilization
time set by the oscillation stabilization time select register (OSTS).
In the following cases, set the oscillation stabilization time of the OSTS register to
the value greater than the count value which is to be checked by the OSTC register
after the oscillation starts.
• If the X1 clock starts oscillation while the high-speed on-chip oscillator clock is
being used as the CPU clock.
• If the STOP mode is entered and then released while the high-speed on-chip
oscillator clock is being used as the CPU clock with the X1 clock oscillating.
(Note, therefore, that only the status up to the oscillation stabilization time set by
the OSTS register is set to the OSTC register after the STOP mode is released.)