RL78/G10 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0384EJ0311 Rev. 3.11 362
Dec 22, 2016
12.5.7 Calculating transfer clock frequency
The transfer clock frequency for 3-wire serial I/O (CSI00, CSI01) communication can be calculated by the following
expressions.
(1) Master
(Transfer clock frequency) = {Operation clock (fMCK) frequency of target channel} ÷ (SDR0nH[7:1] + 1) ÷ 2 [Hz]
(2) Slave
(Transfer clock frequency) = {Frequency of serial clock (SCK) supplied by master}
Note
[Hz]
Note The permissible maximum transfer clock frequency is fMCK/6.
Remark The value of SDR0nH[7:1] is the value of bits 7 to 1 of serial data register 0nH (SDR0nH) (0000000B to
1111111B) and therefore is 0 to 127.
The operation clock (f
MCK) is determined by serial clock select register 0 (SPS0) and bit 7 (CKS0n) of serial mode
register 0n (SMR0nH).
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