RL78/G10 CHAPTER 10 A/D CONVERTER
R01UH0384EJ0311 Rev. 3.11 250
Dec 22, 2016
10.3.5 A/D conversion result lower-order bit storage register (ADCRL)
This register is an 8-bit register that holds the two lower-order bits of the result of 10-bit A/D conversion. The six lower-
order bits are fixed to 0.
The ADCRL register can be read by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 10-8. Format of A/D Conversion Result Lower-Order Bit Storage Register (ADCRL)
Address: FFF1EH After reset: 00H R
Symbol 7 6 5 4 3 2 1 0
ADCRL ADCR1 ADCR0 0 0 0 0 0 0
Figure 10-9 shows the state after the result of 10-bit resolution A/D conversion has been stored. Each time A/D
conversion ends, the conversion result is loaded from the successive approximation register (SAR). The eight higher-order
bits of the conversion result are stored in ADCRH and the two lower-order bits of the result are stored in ADCRL.
Figure 10-9. The State after Storage of the Result of 10-bit Resolution A/D Conversion
ADC
R9
ADC
R8
ADC
R7
ADC
R6
ADC
R5
ADC
R4
ADC
R3
ADC
R2
ADC
R1
ADC
R0
0 0 0 0 0 0
Cautions 1. When writing to the A/D converter mode register 0 (ADM0) and analog input channel
specification register (ADS), the contents of the ADCRH/ADCRL registers may become
undefined. Read the conversion result following conversion completion before writing to
the ADM0 and ADS registers. Using timing other than the above may cause an incorrect
conversion result to be read.
2. When the ADCRL register is read while 8-bit resolution A/D conversion is selected (when
the ADTYP bit of A/D converter mode register 2 (ADM2) is 1), 0 is read from the two
higher-order bits (ADCR1 and ADCR0). Note that, when ADCRL register is read before
completion of A/D conversion while 8-bit resolution A/D conversion is selected, 0 may
not be read from the two higher-order bits (ADCR1, ADCR0).
ADCRH
ADCRL
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