RL78/G10 CHAPTER 11 COMPARATOR
R01UH0384EJ0311 Rev. 3.11 269
Dec 22, 2016
11.3.3 Comparator Filter Control Register (COMPFIR)
This register selects the effective edge for the comparator interrupt signal, and enables or disables the digital filter.
If noise elimination is required, set the C0FCK1 and C0FCK0 bits so that the digital filter is enabled. When the digital
filter is enabled, the comparator output is checked if its level remains the same for three consecutive digital filter sampling
clock cycles.
The COMPFIR register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 11-4. Format of Comparator Filter Control Register (COMPFIR)
Address: FFF61H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
COMPFIR 0 0 0 0 C0EDG C0EPO C0FCK1 C0FCK0
C0EDG C0EPO Effective edge selection for comparator 0 interrupt signal
Note 1
0 0 Rising edge
0 1 Falling edge
1 × Both rising and falling edges
C0FCK1 C0FCK0 Comparator 0 digital filter enable/disable
Notes 1, 2, 3
0 0 Digital filter disabled
0 1 Digital filter enabled, sampling clock: fCLK
1 0 Digital filter enabled, sampling clock: fCLK/8
1 1 Digital filter enabled, sampling clock: fCLK/32
Notes 1. If bit C0EDG, C0EPO, C0FCK1, or C0FCK0 is changed while operation of the comparator 0 is
enabled, a comparator 0 interrupt (INTCMP0) may be generated. Change these bits only after
clearing the C0IE bit in the COMPOCR register to 0 to disable an interrupt request. Also, be sure
to clear bit 2 (CMPIF0) in the interrupt request flag register 1L (IF1L) to 0 after changing these
bits.
2. If bit C0FCK1 or C0FCK0 is changed, a wait period of four cycles of the sampling clock is
required to update the digital filter. To use the comparator 0 interrupt (INTCMP0), set the C0IE
bit in the COMPOCR register to 1 after this wait period.
3. To use the comparator in STOP mode, disable the digital filter (C0FCK1 and C0FCK0 = 00B).
Remark ×: Don't care
<R>
To Next Page
Loading...
Need help?
General
