RL78/G10 CHAPTER 6 TIMER ARRAY UNIT
R01UH0384EJ0311 Rev. 3.11 115
Dec 22, 2016
6.2.2 Timer data register 0n (TDR0n)
The TDR0n register consists of two eight bit registers (TDR0nH, TDR0nL) for which the capture or comparison
functions can be selected.
Switching between the capture and comparison functions is by using the MD0n3 to MD0n0 bits of the timer mode
register 0n (TMR0n) to select the operating mode.
When using the TDR0n register as a compare register, the value of the TDR0nL and TDR0nH registers can be
changed at any time.
For access to a TDR0n register, the TDR0nH and TDR0nL registers must be accessed consecutively.
In eight-bit timer mode (i.e. when the SPLIT0n bit of timer mode register 0n (TMR0n) is set to “1”), the TDR0n register
can be rewritten in eight-bit units, with the higher 8 bits used as TDR0nH and the lower 8 bits used as TDR0nL.
The following points for caution apply when data are read from or written to TDR0nH and TDR0nL registers.
• In 16-bit timer mode (when channels 0 and 2 are in use, or bit 3 (SPLIT0n) of the TMR0nH register of channels 1 and
3 is cleared to “0”)
Writing to TDR0nH and TDR0nL registers must be performed by writing in a row with data in order of that for the
TDR0nH register and that for the TDR0nL register. The values of TDR0nH and TDR0nL are updated when TDR0nL is
rewritten.
Reading from the TDR0nH and TDR0nL registers must be performed in a row with data in order of that from the
TDR0nL register and that from the TDR0nH register. The value of TDR0nH is updated when TDR0nL is read.
If data are written to TDR0nH, read from TDR0nL, or read from TCR0n between the successive read or successive
write operations, reading and writing is not performed correctly.
Consecutive reading from the TDR0nH and TDR0nL registers and consecutive writing to the TDR0nH and TDR0nL
registers must be performed in the state where an interrupt is disabled by the DI instruction.
• In 8-bit timer mode (when bit 3 (SPLIT0n) of the TMR0nH register of channel 1 or 3 is set to “1”)
The data can be written to the TDR0nH and TDR0nL registers in 8-bit units in 8-bit timer mode.
Reading from TDR0nH register must be performed in a row with data in order of that from the TDR0nL register and
that from the TDR0nH register. The value of TDR0nH is updated when TDR0nL is read.
If data are written to TDR0nH, read from TDR0nL, or read from TCR0n between the successive read operations,
reading is not performed correctly.
Consecutive reading from the TDR0nH and TDR0nL registers must be performed in the state where an interrupt is
disabled by the DI instruction.
Remark n: Channel number
n = 0, 1 (for 10-pin products); n = 0 to 3 (for 16-pin products)
Caution When channels 1 and 3 are used in 8-bit timer mode (SPLIT = 1), it is prohibited to read the TCR01H
and TDR01H registers or the TCR03H and TDR03H registers.
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