RL78/G10 CHAPTER 14 INTERRUPT FUNCTIONS
R01UH0384EJ0311 Rev. 3.11 515
Dec 22, 2016
14.4.4 Interrupt request hold
There are instructions where, even if an interrupt request is issued while the instructions are being executed, interrupt
request acknowledgment is held pending until the end of execution of the next instruction. These instructions (interrupt
request hold instructions) are listed below.
• MOV PSW, #byte
• MOV PSW, A
• MOV1 PSW. bit, CY
• SET1 PSW. bit
• CLR1 PSW. bit
• RETB
• RETI
• POP PSW
• BTCLR PSW. bit, $addr20
• EI
• DI
• SKC
• SKNC
• SKZ
• SKNZ
• SKH
• SKNH
• Instructions that write data for the IF0L, IF0H, IF1L, MK0L, MK0H, MK1L, PR00L, PR00H, PR10L, PR10H, PR01L,
and PR11L registers
Figure 14-14 shows the timing at which interrupt requests are held pending.
Figure 14-14. Interrupt Request Hold
Instruction N Instruction M
PSW and PC saved, jump
to interrupt servicing
Interrupt servicing
program
CPU processing
××IF
Remarks 1. Instruction N: Interrupt request hold instruction
2. Instruction M: Instruction other than interrupt request hold instruction
To Next Page
Loading...
