RL78/G10 CHAPTER 4 PORT FUNCTIONS
R01UH0384EJ0311 Rev. 3.11 64
Dec 22, 2016
4.3.4 Port output mode register 0 (POM0)
This register sets CMOS output or N-ch open drain output in 1-bit units.
N-ch open drain output (V
DD tolerant) mode can be selected for the SDA00 pin during simplified I
2
C communication with
an external device.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Caution An on-chip pull-up resistor is not connected to a bit for which N-ch open drain output (V
DD tolerance)
mode (POM0n =1) is set.
Figure 4-4. Format of Port Output Mode Register 0 (POM0)
10-pin products
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
POM0 0 0 0 0 0 0 POM01 POM00 F0050H 00H R/W
16-pin products
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
POM0 POM07 POM06 0 0 0 0 POM01 POM00 F0050H 00H R/W
POM0n P0n pin output mode selection
0 Normal output mode
1 N-ch open-drain output (VDD tolerant) mode
n = 0, 1, 6, 7
Caution Be sure to set bits that are not mounted to their initial values.
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