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Renesas RL78/G10 - Registers Controlling the Comparator; Peripheral Enable Register 0 (PER0)

Renesas RL78/G10
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RL78/G10 CHAPTER 11 COMPARATOR
R01UH0384EJ0311 Rev. 3.11 267
Dec 22, 2016
11.3 Registers Controlling the Comparator
The following lists the registers to control the comparator.
Peripheral enable register 0 (PER0)
Comparator mode setting register (COMPMDR)
Comparator filter control register (COMPFIR)
Comparator output control register (COMPOCR)
Port mode control register 0 (PMC0)
Port mode register 0 (PM0)
Port register 0 (P0)
11.3.1 Peripheral Enable Register 0 (PER0)
This register enables or disables clock supply to each peripheral hardware macro. Clock supply to a hardware macro
that is not used is stopped in order to reduce the power consumption and noise.
When the comparator is used, be sure to set bit 5 (CMPEN) of this register to 1.
The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 11-2. Format of Peripheral Enable Register 0 (PER0)
Address: F00F0H After reset: 00H R/W
Symbol <7> <6> <5> <4> 3 <2> 1 <0>
PER0 TMKAEN
Note
CMPEN
Note
ADCEN IICA0EN
Note
0 SAU0EN 0 TAU0EN
CMPEN Control of comparator input clock
0
Stops input clock supply.
SFR used by the comparator cannot be written.
The comparator is in the reset status.
1
Supplies input clock.
SFR used by the comparator can be read/written.
Note These bits are only available in the 16-pin products.
Cautions 1. When setting the comparator, be sure to set the CMPEN bit to 1 first before setting the
registers shown below. If CMPEN = 0, control registers of the comparator are cleared
to their initial values and writing to them is ignored (except for port mode register 0
(PM0), port register 0 (P0), and port mode control register 0 (PMC0)).
Comparator mode setting register (COMPMDR)
Comparator filter control register (COMPFIR)
Comparator output control register (COMPOCR)
2. Be sure to clear the following bits to 0.
10-pin products: Bits 1, 3, 4, 6, and 7
16-pin products: Bits 1 and 3

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