RL78/G10 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0384EJ0311 Rev. 3.11 300
Dec 22, 2016
12.3.15 Noise filter enable register 0 (NFEN0)
The NFEN0 register is used to set whether the noise filter can be used for the input signal from the serial data input pin
of UART.
Disable the noise filter of the pin used for CSI or simplified I
2
C communication, by clearing the corresponding bit of this
register to 0.
Enable the noise filter of the pin used for UART communication, by setting the corresponding bit of this register to 1.
When the noise filter is enabled, after synchronization with the operating clock (f
MCK) for the target channel, whether the
signal keeps the same value for two clock cycles is detected.
When the noise filter is disabled, the input signal is only synchronized with the operating clock (f
MCK) for the target
channel.
The NFEN0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears the NFEN0 register to 00H.
Figure 12-18. Format of Noise Filter Enable Register 0 (NFEN0)
Address: F0070H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
NFEN0 0 0 0 0 0 0 0 SNFEN00
SNFEN00 Use of noise filter of RxD0 pin
0 Noise filter OFF
1 Noise filter ON
Set the SNFEN00 bit to 1 to use the RxD0 pin.
Clear the SNFEN00 bit to 0 to use other than the RxD0 pin.
Caution Be sure to clear bits 1 to 7 to 0.
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