RL78/G10 CHAPTER 6 TIMER ARRAY UNIT
R01UH0384EJ0311 Rev. 3.11 214
Dec 22, 2016
6.9.4 Operation as multiple PWM output function
By extending the PWM output function and using multiple slave channels, many PWM waveforms with different duty
values can be output. The multiple PWM output function is provided only in the 16-pin products.
When channel 1 or 3 is used as an 8-bit timer (SPLIT0n = 1), only the lower 8-bit timer can be used as the slave
channel for the PWM output function.
For example, when using two slave channels, the period and duty factor of an output pulse can be calculated by the
following expressions.
Pulse period = {Set value of TDR0n (master) + 1} × Count clock period
Duty factor 1 [%] = {Set value of TDR0p (slave 1)}/{Set value of TDR0n (master) + 1} × 100
Duty factor 2 [%] = {Set value of TDR0q (slave 2)}/{Set value of TDR0n (master) + 1} × 100
Remark Although the duty factor exceeds 100% if the set value of TDR0p (slave 1) > {set value of TDR0n (master) +
1} or if the {set value of TDR0q (slave 2)} > {set value of TDR0n (master) + 1}, the actually output PWM
waveform has a 100% duty factor.
The master channel counts the pulse periods. When operated in interval timer mode, it loads the TDR0n value to the
TCR0n register to start counting down.
The slave channel 1 counts the duty factor, and outputs any PWM waveform from the TO0p pin. When operated in
one-count mode, it loads the TDR0p register value to the TCR0p register using INTTM0n from the master channel as a
start trigger, and performs count down operation until TCR0p reaches 0000H. When TCR0p = 0000H, TCR0p outputs
INTTM0p and stops counting with TCR0p = FFFFH until the next start trigger (INTTM0n from the master channel) has
been input.
In the same way as the slave channel 1, the slave channel 2 counts the duty factor, and outputs a desired PWM
waveform from the TO0q pin. When operated in one-count mode, the counter loads the TDR0q register value to the
TCR0q register using INTTM0n from the master channel as a start trigger, and performs counting down until TCR0q
reaches 0000H. When TCR0q = 0000H, the TCR0q register outputs INTTM0q and stops counting with TCR0q = FFFFH
until the next start trigger (INTTM0n from the master channel) has been input.
The PWM output level (TO0p or TO0q) becomes active one count clock (f
TCLK) after generation of INTTM0n from the
master channel, and inactive when TCR0p = 0000H or TCR0q = 0000H.
When channel 0 is used as the master channel as above, up to three types of PWM signals can be output at the same
time.
Cautions 1. To rewrite both timer data register 0n (TDR0nH, TDR0nL) of the master channel and the TDR0pH
and TDR0pL registers of the slave channel, write access is necessary at least four times. Since
the values of the TDR0nH, TDR0nL, TDR0pH, and TDR0pL registers are loaded to the TCR0nH,
TCR0nL, TCR0pH, and TCR0pL registers after INTTM0n is generated from the master channel, if
rewriting is performed separately before and after generation of INTTM0n from the master
channel, the TO0p pin cannot output the expected waveform. To rewrite all of the TDR0nH,
TDR0nL, TDR0pH, and TDR0pL registers, be sure to consecutively rewrite the four registers
immediately after INTTM0n is generated from the master channel.
2. To use the multiple PWM output function in 8-bit timer mode, set 00H in TDR0nH of the master
channel and set the pulse period for the 8-bit timer. The TDR0nL register value should be set
within the range from 00H to FEH (0% to 100% output).
Remark n: Master channel number (n = 0)
p: Channel number of slave channel 1, q: Channel number of slave channel 2
n < p < q ≤ 3 (Where p and q are consecutive integers greater than n)
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