Renesas RL78/G10 - Addressing for Processing Data Addresses; Implied Addressing; Register Addressing

RL78/G10 CHAPTER 3 CPU ARCHITECTURE
R01UH0384EJ0311 Rev. 3.11 44
Dec 22, 2016
3.4 Addressing for Processing Data Addresses
3.4.1 Implied addressing
[Function]
Instructions for accessing registers (such as accumulators) that have special functions are directly specified with the
instruction word, without using any register specification field in the instruction word.
[Operand format]
Implied addressing can be applied only to MULU X.
Figure 3-16. Outline of Implied Addressing
A register
OP code
Memory
Instruction code
(register area)
3.4.2 Register addressing
[Function]
Register addressing accesses a general-purpose register as an operand. The instruction word of 3-bit long is used
to select an 8-bit register and the instruction word of 2-bit long is used to select a 16-bit register.
[Operand format]
Identifier Description
r X, A, C, B, E, D, L, H
rp AX, BC, DE, HL
Figure 3-17. Outline of Register Addressing
Register
OP code
Memory (register bank area)