RL78/G10 CHAPTER 14 INTERRUPT FUNCTIONS
R01UH0384EJ0311 Rev. 3.11 505
Dec 22, 2016
14.3.3 Priority specification flag registers (PR00L, PR00H, PR10L, PR10H, PR01L, PR11L)
The priority specification flag registers are used to set the priority level of the corresponding maskable interrupt.
A priority level is set by using the PR0xy and PR1xy registers in combination (xy = 0L, 0H, 1L).
The PR00L, PR00H, PR10L, PR10H, PR01L, and PR11L registers can be set by a 1-bit or 8-bit memory manipulation
instruction.
Remark If an instruction that writes data to this register is executed, the number of instruction execution clocks
increases by 2 clocks.
Figure 14-6. Format of Priority Specification Flag Registers (PR00L, PR00H, PR10L, PR10H) (10-pin product)
ddress: FFFE8H After reset: FFH R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
PR00L TMPR000 TMPR001H SREPR00 SRPR00
STPR00
CSIPR000
IICPR000
PPR01 PPR00 WDTIPR0
ddress: FFFECH After reset: FFH R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
PR10L TMPR100 TMPR101H SREPR10 SRPR10
STPR10
CSIPR100
IICPR100
PPR11 PPR10 WDTIPR1
ddress: FFFE9H After reset: FFH R/W
Symbol 7 6 5 4 3 <2> <1> <0>
PR00H 1 1 1 1 1 KRPR0 ADPR0 TMPR001
ddress: FFFEDH After reset: FFH R/W
Symbol 7 6 5 4 3 <2> <1> <0>
PR10H 1 1 1 1 1 KRPR1 ADPR1 TMPR101
XXPR1X XXPR0X Priority Level Selection
0 0 Specifying level 0 (high priority)
0 1 Specifying level 1
1 0 Specifying level 2
1 1 Specifying level 3 (low priority)
Caution Do not change undefined bit data.
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