Renesas RL78/G10 - Based Indexed Addressing

RL78/G10 CHAPTER 3 CPU ARCHITECTURE
R01UH0384EJ0311 Rev. 3.11 53
Dec 22, 2016
3.4.8 Based indexed addressing
[Function]
Based indexed addressing uses the contents of a register pair specified with the instruction word as the base
address, and the content of the B register or C register similarly specified with the instruction word as offset address.
The sum of these values is used to specify the target address.
[Operand format]
Identifier Description
−
[HL+B], [HL+C] (only the space from F0000H to FFFFFH is specifiable)
−
ES:[HL+B], ES:[HL+C] (higher 4-bit addresses are specified by the ES register)
Figure 3-31. Example of [HL+B], [HL+C]
FFFFFH
F0000H
rp(HL)
[HL +B], [HL+C]
r(B/C)
OP-code
Offset
Instruction code
<1> <2> <1>
<1>
<2>
<2>
Target memory
Memory
Address of
an array
A pair of registers <1> specifies the address where the target
array of data starts in the 64-Kbyte area from F0000H to
FFFFFH.
Either register <2> specifies an offset within the array to the
target location in memory
Tar g et
array
of data
Other data in
the array
Figure 3-32. Example of ES:[HL+B], ES:[HL+C]
X0000H
rp(HL)
X0000H
ES
ES: [HL +B], ES: [HL +C]
r(B/C)
OP-code
byte
XFFFFH
Tar g et
array
of data
Address of
the array
<3>
The ES register <1> specifies a 64-Kbyte area within the overall
1-Mbyte space as the four higher-order bits, X, of the address range.
A pair of registers <2> specifies the address where the target
array of data starts in the 64-Kbyte area specified in the ES
register <1>.
Either register <3> specifies an offset within the array to the
target location in memory.
Specifies a
64-Kbyte area
Offset
<3>
<3>
<1>
<1> <2> <3> <3><1>
<1>
<2>
<2>
<2>
Target memory
Memory
Instruction code
Other data in
the array