RL78/G10 CHAPTER 15 KEY INTERRUPT FUNCTION
R01UH0384EJ0311 Rev. 3.11 519
Dec 22, 2016
15.3.2 Key return mode register (KRM0)
This register sets the key interrupt mode.
The KRM0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Figure 15-3. Format of Key Return Mode Register (KRM0)
ddress: FFF37H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
KRM0 0 0 KRM05 KRM04 KRM03 KRM02 KRM01 KRM00
Cautions 1. When a key interrupt signal is detected (KRM0n = 1) by selecting the falling edge
(KRMD = 0), pull up the relevant input pins to V
DD by an external resistor. For the
KR1, KR6 to KR9 pins, the internal pull-up resistor can be used by setting the
relevant bits to 1 in the key interrupt input pins PU01 to PU04, PU40, and PU125
(Pull-up resistor option registers 0, 4, 12 (PU0, PU4, PU12)).
2. An interrupt will be generated if the target bit of the KRM0 register is set while a
low level (when KREG = 0)/high level (when KREG = 1) is being input to the key
interrupt input pin. To ignore this interrupt, set the KRM0 register after disabling
interrupt servicing by using the interrupt mask flag. Afterward, clear the interrupt
request flag and enable interrupt servicing.
3. The bits not used in the key interrupt mode can be used as normal ports.
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