Renesas RL78/G10 - System Clock Control Register (CKC)

RL78/G10 CHAPTER 5 CLOCK GENERATOR
R01UH0384EJ0311 Rev. 3.11 80
Dec 22, 2016
5.3.2 System clock control register (CKC)
This register is used to select a main system clock.
The CKC register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Figure 5-3. Format of System Clock Control Register (CKC)
Address: FFFA4H After reset: 00H R/W
Note
Symbol 7 6 <5> <4> 3 2 1 0
CKC 0 0 MCS MCM0 0 0 0 0
MCS Status of Main system clock (fMAIN)
0 High-speed on-chip oscillator clock (fIH)
1 High-speed system clock (fMX)
MCM0 Main system clock (fMAIN) operation control
0 Selects the high-speed on-chip oscillator clock (fIH) as the main system clock (fMAIN)
1 Selects the high-speed system clock (fMX) as the main system clock (fMAIN)
Note Bit 5 is read-only.
Cautions 1. Be sure to clear bits 0 to 3, 6, and 7 to 0.
2. Do not select the high-speed system clock (f
MX) as the main system clock (fMAIN)
before the oscillation stabilization time has elapsed after oscillation of f
MX is
started.
3. When the main system clock (f
MAIN) is changed, the peripheral hardware clock
also changes at the same time. Only change f
MAIN after stopping all peripheral
functions and setting the MCM0 bit.