RL78/G10 CHAPTER 18 SELECTABLE POWER-ON-RESET CIRCUIT
R01UH0384EJ0311 Rev. 3.11 542
Dec 22, 2016
18.3 Operation of Selectable Power-on-reset Circuit
Specify the voltage detection level by using the option byte 000C1H.
The internal reset signal is generated at power on.
The internal reset status is retained until the supply voltage (V
DD) exceeds the voltage detection level (VSPOR). The
internal reset is cleared when the supply voltage (V
DD) exceeds the voltage detection level (VSPOR).
The internal reset is generated when the supply voltage (V
DD) drops lower than the voltage detection level (VSPDR).
Figure 18-2 shows the timing of generation of the internal reset signal by the selectable power-on-reset circuit.
Figure 18-2. Timing of Internal Reset Signal Generation
High-speed on-chip
oscillator clock (f
IH
)
Supply voltage (V
DD
)
High-speedsystem clock (f
MX
)
(when X1 oscillation is selected)
(16-pin products only)
Internal reset signal
Wait for oscillation
accuracy stabilization
Note 1
Reset period
(oscillation
stop)
SPOR reset
processing
time 3.01 ms
(MAX.)
SPOR reset
processing
time 3.01 ms
(MAX.)
Starting oscillation is specified by software
Starting oscillation is specified by software
Note 2
Note 2
Normal operation (high-speed
on-chip oscillator clock)
Normal operation (high-speed
on-chip oscillator clock)
Operation
stops
Operation
stops
Wait for oscillation
accuracy stabilization
Note 1
V
DDDR
V
SPDR
V
SPOR
CPU clock
Notes 1. The internal reset processing time includes the oscillation accuracy stabilization time of the high-speed on-
chip oscillator clock.
2. The high-speed on-chip oscillator clock and a high-speed system clock can be selected as the CPU clock
(16-pin products only). To use the X1 clock, use the oscillation stabilization time counter status register
(OSTC) to confirm the lapse of the oscillation stabilization time.
Remark V
SPOR: SPOR power supply rise detection voltage
V
SPDR: SPOR power supply fall detection voltage
V
DDDR: Data retention lower limit voltage
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