RL78/G10 CHAPTER 6 TIMER ARRAY UNIT
R01UH0384EJ0311 Rev. 3.11 125
Dec 22, 2016
6.3.4 Timer status register 0n (TSR0n)
The TSR0n register indicates the overflow status of the counter of channel n.
The TSR0n register is valid only in the capture mode (MD0n3 to MD0n1 = 010B) and capture & one-count mode
(MD0n3 to MD0n1 = 110B). It will not be set in any other mode. See Table 6-4 for the operation of the OVF bit in each
operation mode and set/clear conditions.
The TSR0n register can be read by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 6-9. Format of Timer Status Register 0n (TSR0n)
Address: F01A0H (TSR00), F01A2H (TSR01) After reset: 00H R
F01A4H (TSR02), F01A6H (TSR03)
Symbol 7 6 5 4 3 2 1 0
TMR00L 0 0 0 0 0 0 0 OVF
OVF Counter overflow status of channel n
0 Overflow does not occur.
1 Overflow occurs.
When OVF = 1, this flag is cleared (OVF = 0) when the next value is captured without overflow.
Remark n: Channel number
n = 0, 1 (for 10-pin products); n = 0 to 3 (for 16-pin products)
Table 6-4. OVF Bit Operation and Set/Clear Conditions in Each Operation Mode
Timer operation mode OVF bit Set/clear conditions
• Capture mode
• Capture & one-count mode
clear When no overflow has occurred upon capturing
set When an overflow has occurred upon capturing
• Interval timer mode
• Event counter mode
• One-count mode
clear
− (Use prohibited)
set
Remark The OVF bit does not change immediately after the counter has overflowed, but changes upon the
subsequent capture.
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