RL78/G10 CHAPTER 16 STANDBY FUNCTION
R01UH0384EJ0311 Rev. 3.11 525
Dec 22, 2016
16.2 Registers controlling standby function
The standby function is controlled by the following registers.
For details of each register, see CHAPTER 5 CLOCK GENERATOR.
Register which enables or stops the operation of the low-speed on-chip oscillator in the HALT or STOP mode.
• Operation speed mode control register (OSMC)
Registers which controls oscillation stabilization time of the X1 clock when the STOP mode is released.
• Oscillation stabilization time counter status register (OSTC)
Note
• Oscillation stabilization time select register (OSTS)
Note
Note 16-pin products only.
16.3 Standby Function Operation
16.3.1 HALT mode
(1) HALT mode
The HALT mode is set by executing the HALT instruction. HALT mode can be set regardless of whether the CPU
clock before the setting was the high-speed system clock (16-pin products only) or the high-speed on-chip oscillator
clock.
The operating statuses in the HALT mode are shown below.
Caution Because the interrupt request signal is used to clear the HALT mode, if the interrupt mask flag is 0
(the interrupt processing is enabled) and the interrupt request flag is 1 (the interrupt request signal is
generated), the HALT mode is not entered even if the HALT instruction is executed in such a
situation.
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