RL78/G10 CHAPTER 5 CLOCK GENERATOR
R01UH0384EJ0311 Rev. 3.11 86
Dec 22, 2016
Figure 5-7. Format of Peripheral Enable Register 0 (PER0) (2/2)
Address: F00F0H After reset: 00H R/W
Symbol <7> <6> <5> <4> 3 <2> 1 <0>
PER0
TMKAEN
Note
CMPEN
Note
ADCEN
IICA0EN
Note
0 SAU0EN 0 TAU0EN
IICA0EN Control of serial interface IICA input clock supply
0
Stops input clock supply.
• SFR used by the serial interface IICA cannot be written.
• The serial interface IICA is in the reset status.
1
Enables input clock supply.
• SFR used by the serial interface IICA can be read and written.
SAU0EN Control of serial array unit input clock supply
0
Stops input clock supply.
• SFR used by the serial array unit cannot be written.
• The serial array unit is in the reset status.
1
Enables input clock supply.
• SFR used by the serial array unit can be read and written.
TAU0EN Control of timer array unit input clock supply
0
Stops input clock supply.
• SFR used by timer array unit cannot be written.
• Timer array unit is in the reset status.
1
Enables input clock supply.
• SFR used by timer array unit can be read and written.
Note 16-pin products only.
Caution Be sure to clear the following bits to 0.
10-pin products: Bits 1, 3, 4, 6, and 7
16-pin products: Bits 1 and 3
5.3.7 Operation speed mode control register (OSMC)
The OSMC register can be used to control supply of the operation clock for the 12-bit interval timer.
When operating the 12-bit interval timer, set WUTMMCK0 = 1 beforehand and do not set WUTMMCK0 = 0 until the
timer is stopped.
The OSMC register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 5-8. Format of Operation Speed Mode Control Register (OSMC)
Address: F00F3H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
OSMC 0 0 0
WUTMMCK0
0 0 0 0
WUTMMCK0
Supply of operation clock for 12-bit interval timer
0 Stops Clock supply
1 Low-speed on-chip oscillator clock (fIL) supply
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