RL78/G10 CHAPTER 6 TIMER ARRAY UNIT
R01UH0384EJ0311 Rev. 3.11 126
Dec 22, 2016
6.3.5 Timer channel enable status register 0 (TE0, TEH0 (8-bit mode))
The TE0 and TEH0 registers are used to enable or stop the timer operation of each channel.
Each bit of the TE0 and TEH0 registers correspond to each bit of the timer channel start register 0 (TS0, TSH0) and the
timer channel stop register 0 (TT0, TTH0). When a bit of the TS0 and TSH0 registers is set to 1, the corresponding bit of
TE0 and TEH0 is set to 1. When a bit of the TT0 and TTH0 registers is set to 1, the corresponding bit of TE0 and TEH0 is
cleared to 0.
The TE0 and TEH0 registers can be read by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears TE0 and TEH0 registers to 00H.
Figure 6-10. Format of Timer Channel Enable Status Register 0 (TE0)
Address: F01B0H After reset: 00H R
Symbol 7 6 5 4 3 2 1 0
TE0 0 0 0 0 TE03
Note
TE02
Note
TE01 TE00
TE0n Indication of operation enable/stop status of channel n
0 Operation is stopped.
1 Operation is enabled.
Indicates operation enable/stop status of the 16-bit timer.
TE01 and TE03 bits indicate whether operation of the lower 8-bit timer is enabled or stopped when channels 1 and
3 are in the 8-bit timer mode.
Note 16-pin products only.
Remark n: Channel number
n = 0, 1 (for 10-pin products); n = 0 to 3 (for 16-pin products)
Figure 6-11. Format of Timer Channel Enable Status Register 0 (TEH0)
Address: F01B1H After reset: 00H R
Symbol 7 6 5 4 3 2 1 0
TEH0 0 0 0 0 TEH03
Note
0 TEH01 0
TEH0n Indication of operation enable/stop status of channel n
0 Operation is stopped.
1 Operation is enabled.
This bit indicates whether operation of the higher 8-bit timer is enabled or stopped when channels 1 and 3 are in the
8-bit timer mode.
Note 16-pin products only.
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