Renesas RL78/G10

RL78/G10 CHAPTER 6 TIMER ARRAY UNIT
R01UH0384EJ0311 Rev. 3.11 141
Dec 22, 2016
6.5.2 Start timing of counter
Timer count register 0n (TCR0n) operation becomes enabled by setting of TS0n bit of timer channel start register 0
(TS0).
Operations from count operation enabled state to timer count register 0n (TCR0n) count start is shown in Table 6-5.
Table 6-5. Operations from Count Operation Enabled State to Timer Count Register 0n (TCR0n) Count Start
Timer operation mode Operation when TS0n = 1 is set
• Interval timer mode
No operation is carried out from start trigger detection (TS0n = 1) until count
clock generation.
The first count clock loads the value of the TDR0n register to the TCR0n register
and the subsequent count clock performs count down operation (see 6.5.3 (1)
Interval timer mode operation).
• Event counter mode
Writing 1 to the TS0n bit loads the value of the TDR0n register to the TCR0n
register.
Detection TI0n input edge, the subsequent count clock performs count down
operation. (see 6.5.3 (2) Event counter mode operation).
• Capture mode
No operation is carried out from start trigger (TS0n = 1) detection until count
clock generation.
The first count clock loads 0000H to the TCR0n register and the subsequent
count clock performs count up operation (see 6.5.3 (3) Capture mode operation
(input pulse interval measurement)).
• One-count mode
The waiting-for-start-trigger state is entered by writing 1 to the TS0n bit while the
timer is stopped (TE0n = 0).
No operation is carried out from start trigger detection until count clock
generation.
The first count clock loads the value of the TDR0n register to the TCR0n register
and the subsequent count clock performs count down operation (see 6.5.3 (4)
One-count mode operation).
• Capture & one-count mode
The waiting-for-start-trigger state is entered by writing 1 to the TS0n bit while the
timer is stopped (TE0n = 0).
No operation is carried out from start trigger detection until count clock
generation.
The first count clock loads 0000H to the TCR0n register and the subsequent
count clock performs count up operation (see 6.5.3 (5) Capture & one-count
mode operation (high-level width is measured)).