RL78/G10 CHAPTER 10 A/D CONVERTER
R01UH0384EJ0311 Rev. 3.11 244
Dec 22, 2016
10.3.1 Peripheral enable register 0 (PER0)
This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware
macro that is not used is stopped in order to reduce the power consumption and noise.
When the A/D converter is used, be sure to set bit 5 (ADCEN) of this register to 1.
The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 10-2. Format of Peripheral Enable Register 0 (PER0)
Address: F00F0H After reset: 00H R/W
Symbol <7> <6> <5> <4> 3 <2> 1 <0>
PER0 TMKAEN
Note
CMPEN
Note
ADCEN IICA0EN
Note
0 SAU0EN 0 TAU0EN
ADCEN Control of A/D converter input clock supply
0
Stops input clock supply.
• SFR used by the A/D converter cannot be written.
• The A/D converter is in the reset status.
1
Enables input clock supply.
• SFR used by the A/D converter can be read/written.
Note 16-pin products only.
Cautions 1. When setting the A/D converter, be sure to set the following registers while the ADCEN
bit is set to 1 first. If ADCEN = 0, the values of the A/D converter control registers are
cleared to their initial values and writing to them is ignored (except for the port mode
register 0 (PM0) and the port mode control register 0 (PMC0)).
• A/D converter mode register 0 (ADM0)
• A/D converter mode register 2 (ADM2)
• A/D conversion result higher-order bit storage register (ADCRH)
• A/D conversion result lower-order bit storage register (ADCRL)
• Analog input channel specification register (ADS)
• A/D test register (ADTES)
2. Be sure to clear the following bits to 0.
10-pin products: Bits 1, 3, 4, 6, and 7
16-pin products: Bits 1 and 3
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