RL78/G10 CHAPTER 6 TIMER ARRAY UNIT
R01UH0384EJ0311 Rev. 3.11 139
Dec 22, 2016
6.5 Operation of Counter
6.5.1 Count clock (f
TCLK)
The count clock (fTCLK) of the timer array unit can be selected between following by CCS0n bit of timer mode register 0n
(TMR0n). .
• Operation clock (f
MCK) specified by the CKS0n1 bit
• Valid edge of input signal input from the TI0n pin
Because the timer array unit is designed to operate in synchronization with f
CLK, the timings of the count clock (fTCLK)
are shown below.
(1) When operation clock (fMCK) specified by the CKS0n1 bit is selected (CCS0n = 0)
The count clock (f
TCLK) is between fCLK to fCLK /2
15
by setting of timer clock select register 0 (TPS0). When a divided
f
CLK is selected, however, the clock selected in TPS0 register is at the high level for one fCLK cycle period from its
rising edge. When a f
CLK is selected, it is fixed to the high level
Counting of timer count register 0n (TCR0n) delayed by one f
CLK cycle period from rising edge of the count clock
(f
TCLK), because of synchronization with fCLK. But, this is described as “counting at rising edge of the count clock
(f
TCLK)”, as a matter of convenience.
Figure 6-22. Timing of f
CLK and Count Clock (fTCLK) (When CCS0n = 0)
Remarks 1. : Rising edge of the count clock (f
TCLK)
: Synchronization, increment/decrement of counter
2. f
CLK: CPU/peripheral hardware clock
fCLK
f
TCLK
( = f
MCK
= CK0n)
fCLK/2
fCLK/4
fCLK/8
fCLK/16
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