RL78/G10 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0384EJ0311 Rev. 3.11 404
Dec 22, 2016
Starting generation of stop condition.
End of IIC communication
Writing 1 to the ST0n bit to clear
(the SE0n bit is cleared to 0)
Writing 0 to the SOE0n bit
Writing 1 to the SO0n bit
Writing 1 to the CKO0n bit
Writing 0 to the SO0n bit
Completion of data
transmission/data reception
Wait
Secure a wait time so that the specifications of
I
2
C on the slave side are satisfied.
Operation stop status
(operable CKO0n manipulation)
Timing to satisfy the low width standard of SCL
for the I
2
C bus.
Output disabled status
(operable SC0n manipulation)
12.7.4 Stop condition generation
After all data are transmitted to or received from the target slave, a stop condition is generated and the bus is released.
(1) Processing flow
Figure 12-96. Timing Chart of Stop Condition Generation
Stop condition
ST0n
SE0n
SOE0n
SCLr output
SDAr output
Operation
stop
SO0n
bit manipulation
CKO0n
bit manipulation
SO0n
bit manipulation
Note
Note During a receive operation, the SOE0n bit of serial output enable register 0 (SOE0) is cleared to 0 before
receiving the last data.
Figure 12-97. Flowchart of Stop Condition Generation
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