RL78/G10 CHAPTER 9 WATCHDOG TIMER
R01UH0384EJ0311 Rev. 3.11 235
Dec 22, 2016
CHAPTER 9 WATCHDOG TIMER
9.1 Functions of Watchdog Timer
The count operation is specified by the user option byte (000C0H) in the watchdog timer.
The watchdog timer operates on the low-speed on-chip oscillator clock.
The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset
signal is generated.
Program loop is detected in the following cases.
• If the watchdog timer counter overflows
• If a 1-bit manipulation instruction is executed on the watchdog timer enable register (WDTE)
• If data other than “ACH” is written to the WDTE register
When a reset occurs due to the watchdog timer, bit 4 (WDTRF) of the reset control flag register (RESF) is set to 1. For
details of the RESF register, see CHAPTER 17 RESET FUNCTION.
When 75% of the overflow time is reached, an interval interrupt is generated.
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